Patents by Inventor Ara Patapoutian

Ara Patapoutian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and apparatuses using a transfer function to predict resistance shifts and/or noise of resistance-based memory
    Patent number: 9349444
    Abstract: Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the transfer function is applied to shift and/or determine a threshold resistance used for at least one of a program operation and a read operation affecting the memory cell. An error rate of the memory cell is reduced as a result.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: May 24, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ara Patapoutian, Ryan James Goss, Antoine Khoueir
  • Load adaptive data recovery pipeline
    Patent number: 9323584
    Abstract: A load adaptive pipeline system includes a data recovery pipeline configured to transfer data between a memory and a host. The pipeline includes a plurality of resources, one or more of the plurality of resources in the pipeline have multiple resource components available for allocation. The system includes a pipeline controller configured to assess at least one parameter affecting data transfer through the pipeline. The pipeline controller is configure to allocate resource components to the one or more resources in the pipeline in response to assessment of the at least one data transfer parameter.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: April 26, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Jeffrey John Pream, Bijoy Purushothaman, Venugopal Rao Garuda, Ara Patapoutian
  • Storage device with multiple coding redundancies
    Patent number: 9312886
    Abstract: A storage device is configured to utilize different encoding and decoding schemes in reading and writing data to different regions of a storage device based on the position of the storage regions and/or component-specific physical characteristics of the regions. Each encoding scheme may include multiple different types of encoders selected based an optimization process for each region.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: April 12, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ara Patapoutian, Deepak Sridhara, Zheng Wang, Jason Charles Jury
  • Mobile personalized boot data
    Patent number: 9299402
    Abstract: A system and associated method of using may generally have at least a mobile data storage device with a controller directing data to first and second tiers of memory. The first tier of memory can have at least boot data pre-fetched from the second tier of memory with the boot data including at least metadata and personalized user data.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: March 29, 2016
    Assignee: Seagate Technology LLC
    Inventors: David Scott Ebsen, Ara Patapoutian, Michael Joseph Steiner, Kevin Arthur Gomez
  • Dynamic distribution of code words among multiple decoders
    Patent number: 9280422
    Abstract: A device comprising a data transfer channel is configured to transfer data between multiple memory devices and a host device. The channel includes multiple decoders and a buffer coupled between the multiple memory devices and the multiple decoders. The buffer is configured to store code words received from the memory devices. Channel control logic is configured to determine availability of one or more of the multiple decoders and to distribute the code words to the one or more decoders based on decoder availability.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: March 8, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Jeffrey John Pream, Ara Patapoutian
  • Variable data recovery scheme hierarchy
    Patent number: 9244766
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: January 26, 2016
    Assignee: Seagate Technology LLC
    Inventors: Ara Patapoutian, Bruce Douglas Buch, Ryan James Goss, Mark Allen Gaertner, Arvind Sridharan
  • MULTI-DIMENTIONAL DATA RANDOMIZATION
    Publication number: 20150378890
    Abstract: The disclosed technology provides for multi-dimensional data randomization in a memory cell array using circular shifts of an initial scrambling sequence. Data addressed to a first row of a data array is randomized using the initial scrambling sequence and data addressed to each row of the memory cell array is randomized using a scrambling sequence that is equal to a circular shift of the initial sequence.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Inventors: Nicholas Odin LIen, Ara Patapoutian, Jeffrey J. Pream, Young Pil Kim, David Orrin Sluiter
  • Memory device with variable code rate
    Patent number: 9201728
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: December 1, 2015
    Assignee: Seagate Technology LLC
    Inventors: Ara Patapoutian, Ryan James Goss, Mark Allen Gaertner, Bruce Douglas Buch, Arvind Sridharan
  • Adaptively combining waveforms
    Patent number: 9195860
    Abstract: A circuit may be configured to adaptively combine two or more waveforms into a single waveform. The circuit can generate weighting factors based on received error signals, and can apply the weighting factors to the two or waveforms to be combined.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: November 24, 2015
    Assignee: Seagate Technology LLC
    Inventors: Ara Patapoutian, Rishi Ahuja, Jason Charles Jury, Raman C Venkataramani
  • ECC management for variable resistance memory cells
    Patent number: 9164832
    Abstract: A data storage device may generally be constructed and operated with at least a controller configured to identify a variance from a predetermined threshold in at least one variable resistance memory cell and upgrade a first error correction code (ECC) level to a second ECC level for the at least one variable resistance memory cell.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: October 20, 2015
    Assignee: Seagate Technology LLC
    Inventors: Mark Allen Gaertner, Ryan James Goss, Antoine Khoueir, Ara Patapoutian
  • Multiuse data channel
    Patent number: 9130596
    Abstract: Presented is a data channel with selectable components, such as encoders or decoders. Also, data having different data signal characteristics can be processed through a data channel based on the data signal characteristics. Further, a data channel may have independent encoding path and an independent decoding path. For example, a first data transmission having first data signal characteristics may be processed via a data channel based on a first selected set of components of the data channel and a second data transmission having second data signal characteristics different than the first data signal characteristics may be processed via the data channel using a second selected set of components in the data channel. The first selected set of components may be different than the second selected set of components, but may share one or more common components.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: September 8, 2015
    Assignee: Seagate Technology LLC
    Inventors: Ara Patapoutian, Hieu V. Nguyen, Prafulla Bollampalli Reddy
  • Opportunistic decoding in memory systems
    Patent number: 9122619
    Abstract: Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: September 1, 2015
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ara Patapoutian, Bernardo Rub, Bruce D. Buch
  • METHODS AND APPARATUSES USING A TRANSFER FUNCTION TO PREDICT RESISTANCE SHIFTS AND/OR NOISE OF RESISTANCE-BASED MEMORY
    Publication number: 20150187413
    Abstract: Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the transfer function is applied to shift and/or determine a threshold resistance used for at least one of a program operation and a read operation affecting the memory cell. An error rate of the memory cell is reduced as a result.
    Type: Application
    Filed: January 13, 2015
    Publication date: July 2, 2015
    Inventors: Ara Patapoutian, Ryan James Goss, Antoine Khoueir
  • Applying a bias signal to memory cells to reverse a resistance shift of the memory cells
    Patent number: 9058869
    Abstract: Data is written to cells of a resistance-based, non-volatile memory. An activity metric is tracked since the writing of the data to the cells. In response to the activity metric satisfying a threshold, a bias signal is applied to the cells to reverse a resistance shift of the cells.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: June 16, 2015
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ara Patapoutian, Antoine Khoueir, Ryan James Goss, Jon D. Trantham
  • ADAPTIVE READ ERROR RECOVERY FOR MEMORY DEVICES
    Publication number: 20150154065
    Abstract: Some embodiments involve a method of detecting an error of a memory device. It is determined whether the detected error is a catastrophic error. If it is determined that the error is a catastrophic error, an error recovery process is bypassed. Some aspects involve a method of detecting an error of a memory device. It is determined whether a counter value is above a predetermined value. If it is determined that the counter value is above the predetermined value an error recovery process is bypassed and a redundant parity recovery process is performed.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 4, 2015
    Applicant: Seagate Technology LLC
    Inventors: Mai A. Ghaly, Ara Patapoutian
  • ADAPTIVE READ ERROR RECOVERY FOR MEMORY DEVICES
    Publication number: 20150154064
    Abstract: An error of a solid-state non-volatile memory is detected. It is determined whether a type of the error is a first type of error. A voltage recovery process is bypassed based on whether the error is the first type of error. If it is determined that the error is a catastrophic error, the voltage error recovery process is bypassed. If it is determined that an offset of a threshold voltage is not greater than a predetermined value, the voltage error recovery process is bypassed.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 4, 2015
    Applicant: Seagate Technology LLC
    Inventors: Mai A. Ghaly, Ara Patapoutian
  • Shifting cell voltage based on grouping of solid-state, non-volatile memory cells
    Patent number: 9042169
    Abstract: Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: May 26, 2015
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Arvind Sridharan, Ara Patapoutian
  • Data detection in adjacent tracks
    Patent number: 9030769
    Abstract: Devices and/or methods may detect data located in adjacent tracks. A signal representative of a first data unit having a higher signal-to-noise ratio may be detected prior to a signal representative of a second data unit having a lower signal-to-noise ratio, and then may be used to improve the signal representative of the second data unit.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 12, 2015
    Assignee: Seagate Technology LLC
    Inventor: Ara Patapoutian
  • Applying a bias signal to memory cells to reverse a resistance shift of the memory cells
    Patent number: 9025359
    Abstract: Data is written to cells of a resistance-based, non-volatile memory. An activity metric is tracked since the writing of the data to the cells. In response to the activity metric satisfying a threshold, a bias signal is applied to the cells to reverse a resistance shift of the cells.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: May 5, 2015
    Assignee: Seagate Technology LLC
    Inventors: Ara Patapoutian, Antoine Khoueir, Ryan James Goss, Jon D. Trantham
  • Read channel throughput management
    Patent number: 9019640
    Abstract: An implementation of a system disclosed herein provides a method of deferring decoding of a data sector received at a read channel of a storage device, in response to determining that a data sector cannot be decoded by a first decoder and storing the data sector for further processing by a second decoder.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: April 28, 2015
    Assignee: Seagate Technology LLC
    Inventors: Prafulla Bollampalli Reddy, Hui Su, Michelle Elaine Blankenship, Eddie Wai Pun, John Marc Wright, Ara Patapoutian, Hieu V. Nguyen