Patents by Inventor Aravind Dasu

Aravind Dasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10964624
    Abstract: A method is provided for removing heat from an integrated circuit package. Fluid coolant is provided from a fluid inlet of a fluid routing device through channels in the fluid routing device to absorb heat generated by first and second integrated circuit dies in the integrated circuit package. The fluid routing device is mounted on a surface of each of the first and second integrated circuit dies. The fluid coolant is provided from the channels to a fluid outlet of the fluid routing device. A flow of the fluid coolant through the fluid routing device is adjusted to reduce a temperature of the first integrated circuit die in response to an increase in a workload of the first integrated circuit die.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Ravi Gutala, Aravind Dasu
  • Publication number: 20200374102
    Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Applicant: Intel Corporation
    Inventors: Peter John McElheny, Aravind Dasu
  • Publication number: 20200328192
    Abstract: A smart network interface controller (NIC) implemented using a stacked die configuration is provided. The NIC may include user-customizable networking circuits formed in a top programmable die and primitive network function blocks formed in a bottom application-specific integrated circuit (ASIC) die. The top programmable die may provide a flexible packet processing pipeline to facilitate efficient control and data communication between the user-customizable networking circuits and the primitive network function blocks. The bottom ASIC die may also include an array of memory blocks operable as lookup tables and intermediate buffers for other network processing circuitry in the NIC. A NIC configured in this way provides both performance, power, and area benefits and superior customer configurability.
    Type: Application
    Filed: June 26, 2020
    Publication date: October 15, 2020
    Applicant: Intel Corporation
    Inventors: Naveed Zaman, Aravind Dasu, Sreedhar Ravipalli, Rakesh Cheerla, Martin Horne
  • Patent number: 10778414
    Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Peter John McElheny, Aravind Dasu
  • Patent number: 10770372
    Abstract: A fluid routing device includes a fluid inlet, first vertical channels, a horizontal channel, a second vertical channel, and a fluid outlet. The first vertical channels are open to the fluid inlet. The horizontal channel is open to each of the first vertical channels. The first vertical channels are oriented to provide fluid coolant from the fluid inlet vertically down to the horizontal channel. The horizontal channel is open on one side such that fluid coolant in the horizontal channel directly contacts an apparatus attached to a bottom of the fluid routing device. The second vertical channel is open to the horizontal channel. The second vertical channel is oriented to provide fluid coolant vertically up away from the horizontal channel. The fluid outlet is open to the second vertical channel such that fluid coolant from the second vertical channel exits the fluid routing device through the fluid outlet.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: September 8, 2020
    Assignee: Altera Corporation
    Inventors: Ravi Gutala, Arif Rahman, Aravind Dasu, Thomas Sarvey, Devdatta Kulkarni
  • Publication number: 20200211969
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Publication number: 20190229888
    Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.
    Type: Application
    Filed: April 1, 2019
    Publication date: July 25, 2019
    Applicant: Intel Corporation
    Inventors: Peter John McElheny, Aravind Dasu
  • Patent number: 10291397
    Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Peter John McElheny, Aravind Dasu
  • Publication number: 20190043782
    Abstract: An integrated circuit package may include one or more integrated circuit dies and reconfigurable constrained vapor bubble (CVB) heat pipe structures formed on the integrated circuit dies. The reconfigurable CVB heat pipe structures may be adjusted using micro-electro-mechanical systems (MEMS) switches. By turning on a MEMS switch, the corresponding heat pipe structure will exhibit a first heat transfer efficiency. By turning off a MEMS switch, the corresponding heat pipe structure will exhibit a second heat transfer efficiency that is less than the first heat transfer efficiency. The reconfigurable CVB heat pipe structures may be statically programmed and/or dynamically adjusted as hot spot locations within the integrated circuit package migrate over time.
    Type: Application
    Filed: May 16, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Sumita Basu, Aravind Dasu, Mahesh A. Iyer
  • Publication number: 20190012116
    Abstract: An integrated circuit package includes a memory integrated circuit die and a coprocessor integrated circuit die that is coupled to the memory integrated circuit die. The coprocessor integrated circuit die has a logic sector that is configured to accelerate a function for a host processor. The logic sector generates an intermediate result of a computation performed as part of the function. The intermediate result is transmitted to and stored in the memory integrated circuit die.
    Type: Application
    Filed: July 10, 2017
    Publication date: January 10, 2019
    Applicant: Intel Corporation
    Inventors: Ravi Gutala, Aravind Dasu
  • Publication number: 20180211900
    Abstract: A method is provided for removing heat from an integrated circuit package. Fluid coolant is provided from a fluid inlet of a fluid routing device through channels in the fluid routing device to absorb heat generated by first and second integrated circuit dies in the integrated circuit package. The fluid routing device is mounted on a surface of each of the first and second integrated circuit dies. The fluid coolant is provided from the channels to a fluid outlet of the fluid routing device. A flow of the fluid coolant through the fluid routing device is adjusted to reduce a temperature of the first integrated circuit die in response to an increase in a workload of the first integrated circuit die.
    Type: Application
    Filed: January 26, 2017
    Publication date: July 26, 2018
    Applicant: Intel Corporation
    Inventors: Ravi Gutala, Aravind Dasu
  • Publication number: 20180176006
    Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.
    Type: Application
    Filed: December 16, 2016
    Publication date: June 21, 2018
    Inventors: Peter John McElheny, Aravind Dasu
  • Publication number: 20180143860
    Abstract: A host processor may utilize a coprocessor to accelerate the performance of a task. Upon receiving a acceleration request from the host processor, the coprocessor may identify and select an available logic sector within the coprocessor that can be used to perform a task associated with the acceleration request. In some cases, the selected logic sector may not be configured to perform the task, in which case the selected logic sector may be reconfigured. The configuration bit stream used to reconfigure the selected logic sector to perform the task may be retrieved from a stacked memory die mounted on the coprocessor, or, if the configuration bit stream is not stored in the stacked memory die, the configuration bit stream may be retrieved from an external memory through the host processor. Load balancing may be performed to dynamically allocate additional logic sectors to time-critical tasks.
    Type: Application
    Filed: November 22, 2016
    Publication date: May 24, 2018
    Inventors: Aravind Dasu, Scott Weber, Jun Pin Tan, Arifur Rahman
  • Publication number: 20180143777
    Abstract: A system may include a host processor, a coprocessor for accelerating tasks received from the host processor, and one or more memory dies mounted to the coprocessor. The coprocessor and the memory die may be part of an integrated circuit package. The memory die may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor over through-silicon vias. Each logic sector may include one or more data registers that are loaded with configuration data from the memory die. Multiple data registers may be loaded with configuration data simultaneously. The configuration data may be loaded onto an array of configuration memory cells using the data registers. Multiple data registers may be pipelined to allow simultaneous loading of configuration data into multiple sub-arrays of the array of configuration memory cells.
    Type: Application
    Filed: November 22, 2016
    Publication date: May 24, 2018
    Inventors: Aravind Dasu, Scott Weber, Jun Pin Tan, Arifur Rahman
  • Publication number: 20180090417
    Abstract: A fluid routing device includes a fluid inlet, first vertical channels, a horizontal channel, a second vertical channel, and a fluid outlet. The first vertical channels are open to the fluid inlet. The horizontal channel is open to each of the first vertical channels. The first vertical channels are oriented to provide fluid coolant from the fluid inlet vertically down to the horizontal channel. The horizontal channel is open on one side such that fluid coolant in the horizontal channel directly contacts an apparatus attached to a bottom of the fluid routing device. The second vertical channel is open to the horizontal channel. The second vertical channel is oriented to provide fluid coolant vertically up away from the horizontal channel. The fluid outlet is open to the second vertical channel such that fluid coolant from the second vertical channel exits the fluid routing device through the fluid outlet.
    Type: Application
    Filed: September 23, 2016
    Publication date: March 29, 2018
    Applicant: Altera Corporation
    Inventors: Ravi Gutala, Arif Rahman, Aravind Dasu, Thomas Sarvey, Devdatta Kulkarni
  • Patent number: 8831287
    Abstract: A computer implemented method for sensing occupancy of a workspace includes creating a difference image that represents luminance differences of pixels in past and current images of the workspace resulting from motion in the workspace, determining motion occurring in regions of the workspace based on the difference image, and altering a workspace environment based at least in part on the determined motion. The method also includes determining which pixels in the difference image represent persistent motion that can be ignored and determining which pixels representing motion in the difference image are invalid because the pixels are isolated from other pixels representing motion.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: September 9, 2014
    Assignee: Utah State University
    Inventors: Aravind Dasu, Dean Mathias, Chenguang Liu, Randy Christensen, Bruce Christensen
  • Publication number: 20140226867
    Abstract: A computer-implemented method for monitoring and controlling a controlled space. The method includes partitioning a controlled space into one or more regions; evaluating motion within the controlled space; determining occupancy within the one or more regions. The method may also include adjusting conditions within the controlled space based on whether the controlled space, or a specific region thereof, is occupied. Corresponding devices and systems are also disclosed herein.
    Type: Application
    Filed: July 19, 2012
    Publication date: August 14, 2014
    Applicant: UTAH STATE UNIVERSITY
    Inventors: Chenguang Liu, Ran Chang, Bruce Christensen, Juan De La Cruz, Pranab Banerjee, Doug Ahlstrom, Aravind Dasu
  • Publication number: 20140163703
    Abstract: A computer implemented method and system for multi-occupant motion tracking and monitoring may include partitioning out of a controlled space one or more interior regions, tracking one or more occupants within the controlled space by collecting a sequence of images of the controlled space, determining from the sequence of images one or more contiguous pixel groupings corresponding to non-persistent motion (referred to as blobs), and generating one or more bounding boxes that encompass each of the contiguous pixel groupings.
    Type: Application
    Filed: July 19, 2012
    Publication date: June 12, 2014
    Applicant: UTAH STATE UNIVERSITY
    Inventors: Ran Chang, Chenguang Liu, Aravind Dasu
  • Patent number: 8710864
    Abstract: A polymorphic systolic array framework that works in conjunction with an embedded microprocessor on an FPGA, that allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms and extendable to more complex applications in the area of aerospace embedded systems.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: April 29, 2014
    Assignee: Utah State University
    Inventors: Aravind Dasu, Robert C. Barnes
  • Publication number: 20140093130
    Abstract: A computer implemented method for sensing occupancy of a workspace includes creating a difference image that represents luminance differences of pixels in past and current images of the workspace resulting from motion in the workspace, determining motion occurring in regions of the workspace based on the difference image, and altering a workspace environment based at least in part on the determined motion. The method also includes determining which pixels in the difference image represent persistent motion that can be ignored and determining which pixels representing motion in the difference image are invalid because the pixels are isolated from other pixels representing motion.
    Type: Application
    Filed: June 8, 2012
    Publication date: April 3, 2014
    Applicant: UTAH STATE UNIVERSITY RESEARCH FOUNDATION
    Inventors: Aravind Dasu, Dean Mathias, Chenguang Liu, Randy Christensen, Bruce Christensen