Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.

Abstract: An integrated circuit package may include one or more integrated circuit dies and reconfigurable constrained vapor bubble (CVB) heat pipe structures formed on the integrated circuit dies. The reconfigurable CVB heat pipe structures may be adjusted using micro-electro-mechanical systems (MEMS) switches. By turning on a MEMS switch, the corresponding heat pipe structure will exhibit a first heat transfer efficiency. By turning off a MEMS switch, the corresponding heat pipe structure will exhibit a second heat transfer efficiency that is less than the first heat transfer efficiency. The reconfigurable CVB heat pipe structures may be statically programmed and/or dynamically adjusted as hot spot locations within the integrated circuit package migrate over time.

Abstract: An integrated circuit package includes a memory integrated circuit die and a coprocessor integrated circuit die that is coupled to the memory integrated circuit die. The coprocessor integrated circuit die has a logic sector that is configured to accelerate a function for a host processor. The logic sector generates an intermediate result of a computation performed as part of the function. The intermediate result is transmitted to and stored in the memory integrated circuit die.

Abstract: A method is provided for removing heat from an integrated circuit package. Fluid coolant is provided from a fluid inlet of a fluid routing device through channels in the fluid routing device to absorb heat generated by first and second integrated circuit dies in the integrated circuit package. The fluid routing device is mounted on a surface of each of the first and second integrated circuit dies. The fluid coolant is provided from the channels to a fluid outlet of the fluid routing device. A flow of the fluid coolant through the fluid routing device is adjusted to reduce a temperature of the first integrated circuit die in response to an increase in a workload of the first integrated circuit die.

Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.

Abstract: A system may include a host processor, a coprocessor for accelerating tasks received from the host processor, and one or more memory dies mounted to the coprocessor. The coprocessor and the memory die may be part of an integrated circuit package. The memory die may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor over through-silicon vias. Each logic sector may include one or more data registers that are loaded with configuration data from the memory die. Multiple data registers may be loaded with configuration data simultaneously. The configuration data may be loaded onto an array of configuration memory cells using the data registers. Multiple data registers may be pipelined to allow simultaneous loading of configuration data into multiple sub-arrays of the array of configuration memory cells.

Abstract: A host processor may utilize a coprocessor to accelerate the performance of a task. Upon receiving a acceleration request from the host processor, the coprocessor may identify and select an available logic sector within the coprocessor that can be used to perform a task associated with the acceleration request. In some cases, the selected logic sector may not be configured to perform the task, in which case the selected logic sector may be reconfigured. The configuration bit stream used to reconfigure the selected logic sector to perform the task may be retrieved from a stacked memory die mounted on the coprocessor, or, if the configuration bit stream is not stored in the stacked memory die, the configuration bit stream may be retrieved from an external memory through the host processor. Load balancing may be performed to dynamically allocate additional logic sectors to time-critical tasks.

Abstract: A fluid routing device includes a fluid inlet, first vertical channels, a horizontal channel, a second vertical channel, and a fluid outlet. The first vertical channels are open to the fluid inlet. The horizontal channel is open to each of the first vertical channels. The first vertical channels are oriented to provide fluid coolant from the fluid inlet vertically down to the horizontal channel. The horizontal channel is open on one side such that fluid coolant in the horizontal channel directly contacts an apparatus attached to a bottom of the fluid routing device. The second vertical channel is open to the horizontal channel. The second vertical channel is oriented to provide fluid coolant vertically up away from the horizontal channel. The fluid outlet is open to the second vertical channel such that fluid coolant from the second vertical channel exits the fluid routing device through the fluid outlet.

Abstract: A computer implemented method for sensing occupancy of a workspace includes creating a difference image that represents luminance differences of pixels in past and current images of the workspace resulting from motion in the workspace, determining motion occurring in regions of the workspace based on the difference image, and altering a workspace environment based at least in part on the determined motion. The method also includes determining which pixels in the difference image represent persistent motion that can be ignored and determining which pixels representing motion in the difference image are invalid because the pixels are isolated from other pixels representing motion.

Abstract: A computer-implemented method for monitoring and controlling a controlled space. The method includes partitioning a controlled space into one or more regions; evaluating motion within the controlled space; determining occupancy within the one or more regions. The method may also include adjusting conditions within the controlled space based on whether the controlled space, or a specific region thereof, is occupied. Corresponding devices and systems are also disclosed herein.

Abstract: A computer implemented method and system for multi-occupant motion tracking and monitoring may include partitioning out of a controlled space one or more interior regions, tracking one or more occupants within the controlled space by collecting a sequence of images of the controlled space, determining from the sequence of images one or more contiguous pixel groupings corresponding to non-persistent motion (referred to as blobs), and generating one or more bounding boxes that encompass each of the contiguous pixel groupings.

Abstract: A polymorphic systolic array framework that works in conjunction with an embedded microprocessor on an FPGA, that allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms and extendable to more complex applications in the area of aerospace embedded systems.

Abstract: A computer implemented method for sensing occupancy of a workspace includes creating a difference image that represents luminance differences of pixels in past and current images of the workspace resulting from motion in the workspace, determining motion occurring in regions of the workspace based on the difference image, and altering a workspace environment based at least in part on the determined motion. The method also includes determining which pixels in the difference image represent persistent motion that can be ignored and determining which pixels representing motion in the difference image are invalid because the pixels are isolated from other pixels representing motion.

Abstract: Iterative repair problems are generally solved using a combinatorial search method such as simulated annealing are addressed with a FPGA-based coarse-grain pipelined architecture to accelerate a simulated annealing based iterative repair-type event scheduling application. Over 99% of the work done by any simulated annealing algorithm is the repeated execution of three high-level steps: (1) generating, (2) evaluating, and (3) determining the acceptability of a new problem solution. A pipelined processor is designed to take advantage of these steps.

Abstract: A polymorphic systolic array framework that works in conjunction with an embedded microprocessor on an FPGA, that allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms and extendable to more complex applications in the area of aerospace embedded systems.

Abstract: A Partial bitstream relocation method to generates source and destination addresses on Field Programmable Gate Arrays. The bitstream from an active source is located and read in a nonintrusive manner, and written to a destination address. The accelerator runs in real time, moving source code on the fly. Code may be altered by mirror inversion for proper placement when necessary.

Abstract: Iterative repair problems are generally solved using a combinatorial search method such as simulated annealing are addressed with a FPGA-based coarse-grain pipelined architecture to accelerate a simulated annealing based iterative repair-type event scheduling application. Over 99% of the work done by any simulated annealing algorithm is the repeated execution of three high-level steps: (1) generating, (2) evaluating, and (3) determining the acceptability of a new problem solution. A pipelined processor is designed to take advantage of these steps.

Abstract: A method of producing a reconfigurable circuit device for running a computer program of moderate complexity such as multimedia processing. Code for the application is compiled into Control Flow Graphs representing distinct parts of the application to be run. From those Control Flow Graphs are extracted basic blocks. The basic blocks are converted to Data Flow Graphs by a compiler utility. From two or more Data Flow Graphs, a largest common subgraph is determined. The largest common subgraph is ASAP scheduled and substituted back into the Data Flow Graphs which also have been scheduled. The separate Data Flow Graphs containing the scheduled largest common subgraph are converted to data paths that are then combined to form code for operating the application. The largest common subgraph is effected in hardware that is shared among the parts of the application from which the Data Flow Graphs were developed.