Abstract: Described herein are variable gain amplifiers that selectively provide variable or tailored impedances at a degeneration block and/or feedback block depending at least in part on a gain mode of the variable gain amplifier. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality.

Abstract: Disclosed herein are signal amplifiers having a plurality of amplifier cores. Individual amplifier cores can be designed for particular gain modes to enhance particular advantages while reducing other disadvantages. The signal amplifier can then switch between amplifier cores when switching gain modes to achieve desired performance characteristics (e.g., improving noise figure or linearity). Examples of signal amplifiers disclosed herein include amplifier architectures with a high gain amplifier core that reduces the noise figure and a linearity boost amplifier core that increases linearity (e.g., for lower gain modes). The disclosed signal amplifiers can also have switchable reference biases to provide targeted bias current matching. The disclosed signal amplifiers can also include degeneration switching blocks for individual amplifier cores to improve signal linearity.

Abstract: Described herein are variable gain amplifiers and multiplexers that embed programmable attenuators into switchable paths that allow signals in a high gain mode to bypass attenuation. This advantageously reduces or eliminates performance penalties in the high gain mode. The programmable attenuators can be configured to improve linearity of the amplification process through pre-LNA attenuation in targeted gain modes. In addition, described herein are variable gain amplifiers with embedded attenuators in a switching network. The attenuators can be embedded onto switches and can be configured to have little or no effect on a noise factor in a high gain mode because the switching network can provide an attenuation bypass in a high gain mode and an attenuation in other gain modes. The programmable attenuators can be embedded onto a multi-input LNA architecture.

Abstract: Described herein are variable gain amplifiers that selectively provide variable or tailored impedances at a degeneration block and/or feedback block depending at least in part on a gain mode of the variable gain amplifier. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality.

Abstract: A hysteretic switching regulator with low output ripple voltage is disclosed herein. A detector and controller is specifically used to adjust a parameter of the hysteretic switching regulator to compensate for changes in one or more of input voltage and desired output voltage to maintain the output ripple voltage within some desired range.

Abstract: A multi-mode line driver circuit designed to be fabricated in a CMOS process and capable of supporting a plurality of operating modes corresponding, for example, to different profiles of communication standards such as xDSL standards. The line driver circuit incorporates integrated mode switches with a two-stage amplifier architecture to relax amplifier requirements by distributing the signal gain into two amplifier stages. Reconfigurable feedback loops are provided to permit design optimization for particular modes of operation (e.g., ADSL and VDSL compliant modes). In one embodiment implemented as a Class-H amplifier, lift amplifier(s) are provided between a first amplifier stage and a second amplifier stage for controlling voltage supply levels of the second amplifier stage. The lift amplifiers may be enabled by voltage threshold detection circuitry that monitors either the input or the output signals of the first amplifier stage depending on the operable transmission mode.

Abstract: A multi-mode line driver circuit designed to be fabricated in a CMOS process and capable of supporting a plurality of operating modes corresponding, for example, to different profiles of communication standards such as xDSL standards. The line driver circuit incorporates integrated mode switches with a two-stage amplifier architecture to relax amplifier requirements by distributing the signal gain into two amplifier stages. Reconfigurable feedback loops are provided to permit design optimization for particular modes of operation (e.g., ADSL and VDSL compliant modes). In one embodiment implemented as a Class-H amplifier, lift amplifier(s) are provided between a first amplifier stage and a second amplifier stage for controlling voltage supply levels of the second amplifier stage. The lift amplifiers may be enabled by voltage threshold detection circuitry that monitors either the input or the output signals of the first amplifier stage depending on the operable transmission mode.