Patents by Inventor Ardavan Niroomand
Ardavan Niroomand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8207570Abstract: Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.Type: GrantFiled: August 6, 2010Date of Patent: June 26, 2012Assignee: Micron Technology, Inc.Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu
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Publication number: 20110316114Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.Type: ApplicationFiled: September 12, 2011Publication date: December 29, 2011Applicant: Micron Technology, Inc.Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
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Patent number: 8039399Abstract: Some embodiments include methods of forming patterns. A first set of features is photolithographically formed over a substrate, and then a second set of features is photolithographically formed over the substrate. At least some of the features of said second set alternate with features of the first set. Spacer material is formed over and between the features of the first and second sets. The spacer material is anisotropically etched to form spacers along the features of the first and second sets. The features of the first and second sets are then removed to leave a pattern of the spacers over the substrate.Type: GrantFiled: October 9, 2008Date of Patent: October 18, 2011Assignee: Micron Technology, Inc.Inventors: Ardavan Niroomand, Gurtej S. Sandhu, Mark Kiehlbauch, Scott Sills
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Patent number: 8030217Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.Type: GrantFiled: April 30, 2010Date of Patent: October 4, 2011Assignee: Micron Technology, Inc.Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
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Patent number: 8003310Abstract: A template comprising pitch multiplied and non-pitch multiplied features is configured for use in imprint lithography. On a first substrate, a first pattern is formed using pitch multiplication and a second pattern is formed using photolithography without pitch multiplication. The first pattern and the second pattern are transferred to a template. The template is brought into contact with a transfer layer overlying a series of mask layers overlying a second substrate. The pitch multiplied and non-pitch multiplied patterns on the template are transferred to the transfer layer, forming an imprinted pattern. The imprinted pattern is transferred to the second substrate to form pitch multiplied and non-pitch multiplied features.Type: GrantFiled: April 24, 2006Date of Patent: August 23, 2011Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Ardavan Niroomand
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Patent number: 7902074Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels in a device array region. The method further comprises depositing an oxide material over the plurality of mandrels and over a device peripheral region. The method further comprises forming a pattern of photoresist material over the oxide material in the device peripheral region. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces in the device array region. The method further comprises selectively etching photoresist material from the device array region and from the device peripheral region.Type: GrantFiled: April 7, 2006Date of Patent: March 8, 2011Assignee: Micron Technology, Inc.Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
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Publication number: 20110008970Abstract: The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.Type: ApplicationFiled: September 20, 2010Publication date: January 13, 2011Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu, Luan C. Tran
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Patent number: 7867843Abstract: A process may include forming a polysilicon pinnacle above and on a polysilicon island and further forming a floating gate from the polysilicon pinnacle and polysilicon island. The floating gate can bear an inverted T-shape. The floating gate can also be disposed above an isolated semiconductive substrate such as in a shallow-trench isolation semiconductive substrate. Electronic devices may include the floating gate as part of a field effect transistor.Type: GrantFiled: December 22, 2006Date of Patent: January 11, 2011Assignee: Intel CorporationInventors: Ramakanth Alapati, Ardavan Niroomand
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Publication number: 20100295114Abstract: Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.Type: ApplicationFiled: August 6, 2010Publication date: November 25, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu
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Patent number: 7821142Abstract: An alignment mark mask element protects an underlying alignment mark during subsequent processing of a fabrication substrate. The alignment mark mask element is formed concurrent with formation of a photomask from a dual-tone photoresist that exhibits a pattern reversal upon exposure to an energy level. A portion of the dual-tone photoresist above the alignment mark is exposed to an energy sufficient to reverse a positive tone resist to a negative tone, which remains above the alignment mark after developing. The remainder of the dual-tone photoresist is exposed through a reticle at a lesser energy level and patterned to define aperture locations of a photomask for formation of semiconductor device features. In addition, a photomask for use on a fabrication substrate and an intermediate semiconductor device are disclosed. Methods of forming a photomask and an intermediate semiconductor device structure are also disclosed.Type: GrantFiled: June 24, 2008Date of Patent: October 26, 2010Assignee: Micron Technology, Inc.Inventors: Richard D. Holscher, Ardavan Niroomand
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Patent number: 7799694Abstract: The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings. The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.Type: GrantFiled: April 11, 2006Date of Patent: September 21, 2010Assignee: Micron Technology, Inc.Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu, Luan C. Tran
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Patent number: 7790360Abstract: Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.Type: GrantFiled: March 5, 2007Date of Patent: September 7, 2010Assignee: Micron Technology, Inc.Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu
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Publication number: 20100216307Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.Type: ApplicationFiled: April 30, 2010Publication date: August 26, 2010Applicant: Micron Technology, Inc.Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
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Patent number: 7732343Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.Type: GrantFiled: May 3, 2007Date of Patent: June 8, 2010Assignee: Micron Technology, Inc.Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
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Publication number: 20100112818Abstract: Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.Type: ApplicationFiled: January 13, 2010Publication date: May 6, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Baosuo Zhou, Gurtej S. Sandhu, Ardavan Niroomand
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Publication number: 20100093175Abstract: Some embodiments include methods of forming patterns. A first set of features is photolithographically formed over a substrate, and then a second set of features is photolithographically formed over the substrate. At least some of the features of said second set alternate with features of the first set. Spacer material is formed over and between the features of the first and second sets. The spacer material is anisotropically etched to form spacers along the features of the first and second sets. The features of the first and second sets are then removed to leave a pattern of the spacers over the substrate.Type: ApplicationFiled: October 9, 2008Publication date: April 15, 2010Inventors: Ardavan Niroomand, Gurtej S. Sandhu, Mark Kiehlbauch, Scott Sills
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Patent number: 7659208Abstract: Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.Type: GrantFiled: December 6, 2007Date of Patent: February 9, 2010Assignee: Micron Technology, IncInventors: Baosuo Zhou, Gurtej S. Sandhu, Ardavan Niroomand
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Publication number: 20090294878Abstract: The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact with the metal silicide layer. The present invention also includes a gate stack which encompasses a polysilicon layer over a substrate, a metal silicide layer over the polysilicon layer, an antireflective material layer over the metal silicide layer, a silicon nitride layer over the antireflective material layer, and a layer of photoresist over the silicon nitride layer, for photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist and transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer. The patterned silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer encompass a gate stack.Type: ApplicationFiled: August 7, 2009Publication date: December 3, 2009Inventors: Zhiping Yin, Ravi Iyer, Thomas R. Glass, Richard Holscher, Ardavan Niroomand, Linda K. Somerville, Gurtej S. Sandhu
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Patent number: 7576400Abstract: The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact with the metal silicide layer. The present invention also includes a gate stack which encompasses a polysilicon layer over a substrate, a metal silicide layer over the polysilicon layer, an antireflective material layer over the metal silicide layer, a silicon nitride layer over the antireflective material layer, and a layer of photoresist over the silicon nitride layer, for photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist and transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer. The patterned silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer encompass a gate stack.Type: GrantFiled: April 26, 2000Date of Patent: August 18, 2009Assignee: Micron Technology, Inc.Inventors: Zhiping Yin, Ravi Iyer, Thomas R. Glass, Richard Holscher, Ardavan Niroomand, Linda K. Somerville, Gurtej S. Sandhu
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Publication number: 20090149026Abstract: Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.Type: ApplicationFiled: December 6, 2007Publication date: June 11, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Baosuo Zhou, Gurtej S. Sandhu, Ardavan Niroomand