Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth long distance communication, e.g. photonic or electronic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication.

Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a processing unit; a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and/or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices for transferring the data therebetween.

Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication and augment existing memory systems to allow them to be both high capacity and high bandwidth simultaneously.

Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication.

Abstract: An apparatus includes a lithium niobate (LN) layer, and a planar electro-optical modulator having at least one hybrid optical core segment formed of a portion of the LN layer and an optical guiding rib. The optical guiding rib may be located in a top silicon layer of a silicon photonics (SiP) chip, to which a thin-film LN chip is flip-chip mounted, and may be coupled to optical waveguide cores in a first silicon core layer of the SiP chip. One or more drive electrodes are disposed between a substrate of the SiP chip and the LN layer. In some embodiments hybrid optical core segments may include silicon nitride core segments and may form an MZM configured to be differentially or dual-differentially driven.

Abstract: A photonic chip includes a device layer and a port layer, with an optical port located at the port layer. Inter-layer optical couplers are provided for coupling light between the device and port layers. The inter-layer couplers may be configured to couple signal light but block pump light or other undesired wavelength from entering the device layer, operating as an input filter. The port layer may accommodate other light pre-processing functions, such as optical power splitting, that are undesirable in the device layer.

Abstract: An underfill adhesive may be used to mechanically stabilize a photonic integrated circuit chip (PIC) onto an electrical substrate; however, when the PIC is optically coupled to an external optical fiber at or near an edge of the chip, e.g. using an edge coupler, the underfill may flow into the optical interface impacting optical coupling quality. A photonic integrated circuit apparatus according to the disclosure comprises an electrical substrate, which includes a cavity underneath the edge coupler for preventing underfill material from entering the optical interface by impeding capillary action thereof.

Abstract: An underfill adhesive may be used to mechanically stabilize a photonic integrated circuit chip (PIC) onto an electrical substrate; however, when the PIC is optically coupled to an external optical fiber at or near an edge of the chip, e.g. using an edge coupler, the underfill may flow into the optical interface impacting optical coupling quality. A photonic integrated circuit apparatus according to the disclosure comprises an electrical substrate, which includes a cavity underneath the edge coupler for preventing underfill material from entering the optical interface by impeding capillary action thereof.

Abstract: A metal-contact-free photodetector includes an optically absorbing material, e.g. germanium, mounted on a device layer of a photonic integrated circuit, which includes a p-type contact and an n-type contact on opposite sides of a waveguide. The contacts are comprise of a plurality of independently doped regions ranging from lowest doped adjacent the waveguide to highest doped remote from the waveguide. An additional element is to add p and/or n doping on one or more of the sidewalls of the optically absorbing material, e.g Germanium. The advantage compared to the previously disclosed metal-contact-free photodetectors is that the bandwidth is much higher, and full speed is attained at lower voltage.

Abstract: A metal-contact-free photodetector includes an optically absorbing material, e.g. germanium, mounted on a device layer of a photonic integrated circuit, which includes a p-type contact and an n-type contact on opposite sides of a waveguide. The contacts are comprise of a plurality of independently doped regions ranging from lowest doped adjacent the waveguide to highest doped remote from the waveguide. An additional element is to add p and/or n doping on one or more of the sidewalls of the optically absorbing material, e.g Germanium. The advantage compared to the previously disclosed metal-contact-free photodetectors is that the bandwidth is much higher, and full speed is attained at lower voltage.

Abstract: A Ge-on-Si photodetector constructed without doping or contacting Germanium by metal is described. Despite the simplified fabrication process, the device has responsivity of 1.24 A/W, corresponding to 99.2% quantum efficiency. Dark current is 40 nA at ?4 V reverse bias. 3-dB bandwidth is 30 GHz.

Abstract: Conventional hybrid photonic integrated circuits (PIC) combine one type of semiconductor platform for the main PIC, and a different type of semiconductor platform for a secondary chip. Conventional mounting processes include forming a recess in the main PIC, and mating electrical connectors from the secondary chip and the main PIC within the recess. Mating the first and second electrical connectors in the recess increases the complexity of forming the main PIC, and hampers heat dissipation from secondary chip through oxide layers in the main PIC. Providing a conductive, e.g. redistribution, layer from the first electrode along the bottom and sides of the recess eliminates the complexity in forming the main PIC, and enables the first electrical connector to be mounted directly onto a more thermally conductive substrate material.

Abstract: Conventional hybrid photonic integrated circuits (PIC) combine one type of semiconductor platform for the main PIC, and a different type of semiconductor platform for a secondary chip. Conventional mounting processes include forming a recess in the main PIC, and mating electrical connectors from the secondary chip and the main PIC within the recess. Mating the first and second electrical connectors in the recess increases the complexity of forming the main PIC, and hampers heat dissipation from secondary chip through oxide layers in the main PIC. Providing a conductive, e.g. redistribution, layer from the first electrode along the bottom and sides of the recess eliminates the complexity in forming the main PIC, and enables the first electrical connector to be mounted directly onto a more thermally conductive substrate material.

Abstract: A test system for determining a surface characteristic of a chip facet comprises a chip, which has a facet and includes a waveguide, a detector, and a processor. The on-chip waveguide is configured to direct test light towards the facet, where a portion of the test light is reflected and a portion of the test light is transmitted. The detector is configured to measure an amount of the reflected portion or the transmitted portion, and the processor is configured to determine a surface characteristic of the facet, such as a facet angle, a facet curvature, and/or a facet roughness, on the basis of the measured amount.

Abstract: A composite optical waveguide is constructed using an array of waveguide cores, in which one core is tapered to a larger dimension, so that all the cores are used as a composite input port, and the one larger core is used as an output port. In addition, transverse couplers can be fabricated in a similar fashion. The waveguide cores are preferably made of SiN. In some cases, a layer of SiN which is provided as an etch stop is used as at least one of the waveguide cores. The waveguide cores can be spaced away from a semiconductor layer so as to minimize loses.

Abstract: A Ge-on-Si photodetector constructed without doping or contacting Germanium by metal is described. Despite the simplified fabrication process, the device has responsivity of 1.24 A/W, corresponding to 99.2% quantum efficiency. Dark current is 40 nA at ?4 V reverse bias. 3-dB bandwidth is 30 GHz.

Abstract: A skew compensation apparatus and method. In an optical system that uses optical signals, skew may be generated as the optical signals are processed from an input optical signal to at least two electrical signals representative of the phase-differentiated optical signals. A compensation of the skew is provided by including an optical delay line in the path of the optical signal that does not suffer the skew (e.g., that serves as the time base for the skew measurement). The optical delay line introduces a delay Tskew equal to the delay suffered by the optical signal that is not taken as the time base. The two signals are thereby corrected for skew.

Abstract: A test system for determining a surface characteristic of a chip facet comprises a chip, which has a facet and includes a waveguide, a detector, and a processor. The on-chip waveguide is configured to direct test light towards the facet, where a portion of the test light is reflected and a portion of the test light is transmitted. The detector is configured to measure an amount of the reflected portion or the transmitted portion, and the processor is configured to determine a surface characteristic of the facet, such as a facet angle, a facet curvature, and/or a facet roughness, on the basis of the measured amount.

Abstract: A skew compensation apparatus and method. In an optical system that uses optical signals, skew may be generated as the optical signals are processed from an input optical signal to at least two electrical signals representative of the phase-differentiated optical signals. A compensation of the skew is provided by including an optical delay line in the path of the optical signal that does not suffer the skew (e.g., that serves as the time base for the skew measurement). The optical delay line introduces a delay Tskew equal to the delay suffered by the optical signal that is not taken as the time base. The two signals are thereby corrected for skew.

Abstract: A photonic chip includes a device layer and a port layer, with an optical port located at the port layer. Inter-layer optical couplers are provided for coupling light between the device and port layers. The inter-layer couplers may be configured to couple signal light but block pump light or other undesired wavelength from entering the device layer, operating as an input filter. The port layer may accommodate other light pre-processing functions, such as optical power splitting, that are undesirable in the device layer.