Patents by Inventor Ari Novack

Ari Novack has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12287538
    Abstract: An apparatus includes a lithium niobate (LN) layer, and a planar electro-optical modulator having at least one hybrid optical core segment formed of a portion of the LN layer and an optical guiding rib. The optical guiding rib may be located in a top silicon layer of a silicon photonics (SiP) chip, to which a thin-film LN chip is flip-chip mounted, and may be coupled to optical waveguide cores in a first silicon core layer of the SiP chip. One or more drive electrodes are disposed between a substrate of the SiP chip and the LN layer. In some embodiments hybrid optical core segments may include silicon nitride core segments and may form an MZM configured to be differentially or dual-differentially driven.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: April 29, 2025
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Ruizhi Shi, Ari Novack, Alexander Rylyakov, Eu-Jin Andy Lim
  • Patent number: 12117930
    Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a processing unit; a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and/or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices for transferring the data therebetween.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: October 15, 2024
    Assignee: Luminous Computing, Inc.
    Inventors: David Cureton Baker, Ari Novack, Donovan Popps, Benjamin Wiley Melton, Bryan Cope, Mark Baur, Anahita Shayesteh
  • Patent number: 12099724
    Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: September 24, 2024
    Assignee: Luminous Computing, Inc.
    Inventors: David Cureton Baker, Ari Novack, Donovan Popps, Benjamin Wiley Melton, Bryan Cope, Mark Baur, Anahita Shayesteh
  • Publication number: 20240302595
    Abstract: A photonic chip is especially sensitive to damp heat, because the encapsulation oxides that are used in standard wafer fabrication are typically deposited at lower temperatures and are of lesser quality. Accordingly, atomic layer deposition (ALD) is used to deposit a multi-layer, thin-film stack comprising alternating layers of dielectric layers and moisture barrier layers, e.g. metal oxide or semiconductor nitride, thin enough to be optically compatible with optical input/outputs, such as optical edge couplers in or on the chip. The ALD deposited layers are of high quality and protect the moisture sensitive oxide forming the majority of layers in the chip.
    Type: Application
    Filed: March 4, 2024
    Publication date: September 12, 2024
    Inventors: Alexandre HORTH, Michael HOCHBERG, Ari NOVACK, Jiabao ZHENG, Matthew STRESHINSKY
  • Publication number: 20240078175
    Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a processing unit; a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and/or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices for transferring the data therebetween.
    Type: Application
    Filed: January 13, 2023
    Publication date: March 7, 2024
    Inventors: David Cureton BAKER, Ari NOVACK, Donovan POPPS, Benjamin Wiley MELTON, Bryan COPE, Mark BAUR, Anahita SHAYESTEH
  • Publication number: 20240077781
    Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication and augment existing memory systems to allow them to be both high capacity and high bandwidth simultaneously.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 7, 2024
    Inventors: Mitchell A NAHMIAS, Michael J. HOCHBERG, Thomas W. BAEHR-JONES, Ari NOVACK, David Cureton BAKER, Matthew CHANG, Lei WANG, Matthew STRESHINSKY, Wuchun WU, Hamidreza NAHAVANDI, Brian West
  • Publication number: 20240079081
    Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth long distance communication, e.g. photonic or electronic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication.
    Type: Application
    Filed: September 29, 2023
    Publication date: March 7, 2024
    Inventors: David Cureton BAKER, Ari NOVACK, Donovan POPPS, Benjamin Wiley MELTON, Bryan COPE, Mark BAUR, Anahita SHAYESTEH
  • Publication number: 20240078016
    Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication.
    Type: Application
    Filed: December 30, 2022
    Publication date: March 7, 2024
    Inventors: David Cureton BAKER, Ari NOVACK, Donovan POPPS, Benjamin Wiley MELTON, Bryan COPE, Mark BAUR, Anahita SHAYESTEH
  • Publication number: 20230055077
    Abstract: An apparatus includes a lithium niobate (LN) layer, and a planar electro-optical modulator having at least one hybrid optical core segment formed of a portion of the LN layer and an optical guiding rib. The optical guiding rib may be located in a top silicon layer of a silicon photonics (SiP) chip, to which a thin-film LN chip is flip-chip mounted, and may be coupled to optical waveguide cores in a first silicon core layer of the SiP chip. One or more drive electrodes are disposed between a substrate of the SiP chip and the LN layer. In some embodiments hybrid optical core segments may include silicon nitride core segments and may form an MZM configured to be differentially or dual-differentially driven.
    Type: Application
    Filed: August 18, 2022
    Publication date: February 23, 2023
    Inventors: Ruizhi SHI, Ari NOVACK, Alexander RYLYAKOV, Eu-Jin Andy LIM
  • Patent number: 11409036
    Abstract: A photonic chip includes a device layer and a port layer, with an optical port located at the port layer. Inter-layer optical couplers are provided for coupling light between the device and port layers. The inter-layer couplers may be configured to couple signal light but block pump light or other undesired wavelength from entering the device layer, operating as an input filter. The port layer may accommodate other light pre-processing functions, such as optical power splitting, that are undesirable in the device layer.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: August 9, 2022
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Ari Novack, Ruizhi Shi, Alexandre Horth, Ran Ding, Michael J. Hochberg
  • Patent number: 11280971
    Abstract: An underfill adhesive may be used to mechanically stabilize a photonic integrated circuit chip (PIC) onto an electrical substrate; however, when the PIC is optically coupled to an external optical fiber at or near an edge of the chip, e.g. using an edge coupler, the underfill may flow into the optical interface impacting optical coupling quality. A photonic integrated circuit apparatus according to the disclosure comprises an electrical substrate, which includes a cavity underneath the edge coupler for preventing underfill material from entering the optical interface by impeding capillary action thereof.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: March 22, 2022
    Assignee: Nokia Solutions and Networks Oy
    Inventor: Ari Novack
  • Publication number: 20220043222
    Abstract: An underfill adhesive may be used to mechanically stabilize a photonic integrated circuit chip (PIC) onto an electrical substrate; however, when the PIC is optically coupled to an external optical fiber at or near an edge of the chip, e.g. using an edge coupler, the underfill may flow into the optical interface impacting optical coupling quality. A photonic integrated circuit apparatus according to the disclosure comprises an electrical substrate, which includes a cavity underneath the edge coupler for preventing underfill material from entering the optical interface by impeding capillary action thereof.
    Type: Application
    Filed: August 10, 2020
    Publication date: February 10, 2022
    Inventor: Ari Novack
  • Patent number: 10901150
    Abstract: A metal-contact-free photodetector includes an optically absorbing material, e.g. germanium, mounted on a device layer of a photonic integrated circuit, which includes a p-type contact and an n-type contact on opposite sides of a waveguide. The contacts are comprise of a plurality of independently doped regions ranging from lowest doped adjacent the waveguide to highest doped remote from the waveguide. An additional element is to add p and/or n doping on one or more of the sidewalls of the optically absorbing material, e.g Germanium. The advantage compared to the previously disclosed metal-contact-free photodetectors is that the bandwidth is much higher, and full speed is attained at lower voltage.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: January 26, 2021
    Assignee: Elenion Technologies, LLC
    Inventors: Ari Novack, Yaojia Chen
  • Publication number: 20200393618
    Abstract: A metal-contact-free photodetector includes an optically absorbing material, e.g. germanium, mounted on a device layer of a photonic integrated circuit, which includes a p-type contact and an n-type contact on opposite sides of a waveguide. The contacts are comprise of a plurality of independently doped regions ranging from lowest doped adjacent the waveguide to highest doped remote from the waveguide. An additional element is to add p and/or n doping on one or more of the sidewalls of the optically absorbing material, e.g Germanium. The advantage compared to the previously disclosed metal-contact-free photodetectors is that the bandwidth is much higher, and full speed is attained at lower voltage.
    Type: Application
    Filed: June 12, 2019
    Publication date: December 17, 2020
    Inventors: Ari Novack, Yaojia Chen
  • Patent number: 10847665
    Abstract: A Ge-on-Si photodetector constructed without doping or contacting Germanium by metal is described. Despite the simplified fabrication process, the device has responsivity of 1.24 A/W, corresponding to 99.2% quantum efficiency. Dark current is 40 nA at ?4 V reverse bias. 3-dB bandwidth is 30 GHz.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: November 24, 2020
    Assignee: Elenion Technologies, LLC
    Inventors: Thomas Baehr-Jones, Yi Zhang, Michael J. Hochberg, Ari Novack
  • Patent number: 10816740
    Abstract: Conventional hybrid photonic integrated circuits (PIC) combine one type of semiconductor platform for the main PIC, and a different type of semiconductor platform for a secondary chip. Conventional mounting processes include forming a recess in the main PIC, and mating electrical connectors from the secondary chip and the main PIC within the recess. Mating the first and second electrical connectors in the recess increases the complexity of forming the main PIC, and hampers heat dissipation from secondary chip through oxide layers in the main PIC. Providing a conductive, e.g. redistribution, layer from the first electrode along the bottom and sides of the recess eliminates the complexity in forming the main PIC, and enables the first electrical connector to be mounted directly onto a more thermally conductive substrate material.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: October 27, 2020
    Assignee: Elenion Technologies, LLC
    Inventors: Ari Novack, Saeed Fathololoumi, Michael Caverley
  • Publication number: 20200249405
    Abstract: Conventional hybrid photonic integrated circuits (PIC) combine one type of semiconductor platform for the main PIC, and a different type of semiconductor platform for a secondary chip. Conventional mounting processes include forming a recess in the main PIC, and mating electrical connectors from the secondary chip and the main PIC within the recess. Mating the first and second electrical connectors in the recess increases the complexity of forming the main PIC, and hampers heat dissipation from secondary chip through oxide layers in the main PIC. Providing a conductive, e.g. redistribution, layer from the first electrode along the bottom and sides of the recess eliminates the complexity in forming the main PIC, and enables the first electrical connector to be mounted directly onto a more thermally conductive substrate material.
    Type: Application
    Filed: February 1, 2019
    Publication date: August 6, 2020
    Inventors: ARI NOVACK, SAEED FATHOLOLOUMI, MICHAEL CAVERLEY
  • Publication number: 20200225168
    Abstract: A test system for determining a surface characteristic of a chip facet comprises a chip, which has a facet and includes a waveguide, a detector, and a processor. The on-chip waveguide is configured to direct test light towards the facet, where a portion of the test light is reflected and a portion of the test light is transmitted. The detector is configured to measure an amount of the reflected portion or the transmitted portion, and the processor is configured to determine a surface characteristic of the facet, such as a facet angle, a facet curvature, and/or a facet roughness, on the basis of the measured amount.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Inventors: Matthew Akio Streshinsky, Ari Novack, Michael J. Hochberg
  • Patent number: 10677991
    Abstract: A composite optical waveguide is constructed using an array of waveguide cores, in which one core is tapered to a larger dimension, so that all the cores are used as a composite input port, and the one larger core is used as an output port. In addition, transverse couplers can be fabricated in a similar fashion. The waveguide cores are preferably made of SiN. In some cases, a layer of SiN which is provided as an etch stop is used as at least one of the waveguide cores. The waveguide cores can be spaced away from a semiconductor layer so as to minimize loses.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: June 9, 2020
    Assignee: Elenion Technologies, LLC
    Inventors: Ari Novack, Ruizhi Shi, Michael J. Hochberg, Thomas Baehr-Jones
  • Publication number: 20200168750
    Abstract: A Ge-on-Si photodetector constructed without doping or contacting Germanium by metal is described. Despite the simplified fabrication process, the device has responsivity of 1.24 A/W, corresponding to 99.2% quantum efficiency. Dark current is 40 nA at ?4 V reverse bias. 3-dB bandwidth is 30 GHz.
    Type: Application
    Filed: November 29, 2019
    Publication date: May 28, 2020
    Inventors: Thomas Baehr-Jones, Yi Zhang, Michael J. Hochberg, Ari Novack