Patents by Inventor Ariel Almog

Ariel Almog has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12079029
    Abstract: A network adapter includes a network port for communicating with a communication network, a hardware clock, and circuitry. The circuitry is coupled to receive from the communication network, via the network port, one or more time-protocol packets that convey a network time used for synchronizing network devices in the communication network, to align the hardware clock to the network time conveyed in the time-protocol packets, and to make the network time available to one or more time-service consumers running in a host served by the network adapter.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: September 3, 2024
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Itai Levy, Dotan David Levi, Nir Nitzani, Natan Manevich, Alex Vaynman, Ariel Almog
  • Publication number: 20240281292
    Abstract: A device includes a transceiver coupled to a processing device. The processing device is to determine a first time for executing an operation associated with a work execution agent of a plurality of work execution agent. The processing device is further to receive a latency measurement associated with the work execution agent responsive to transmitting the request. The latency measurement is calculated after executing a previous operation associated with the work execution agent at the device. The processing device is also to modify the first time to a second time for executing the operation responsive to receiving the latency measurement.
    Type: Application
    Filed: February 16, 2023
    Publication date: August 22, 2024
    Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Shay Aisman, Ariel Almog, Eliel Peretz, Igor Voks
  • Publication number: 20240231984
    Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.
    Type: Application
    Filed: December 5, 2022
    Publication date: July 11, 2024
    Inventors: Natan Manevich, Dotan David Levi, Shay Aisman, Ariel Almog, Ran Avraham Koren
  • Patent number: 12028155
    Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: July 2, 2024
    Assignee: Mellanox Technologies, LTD.
    Inventors: Bar Shapira, Ariel Almog, Dotan David Levi, Natan Manevich, Thomas Kernen, Liron Mula
  • Publication number: 20240154712
    Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 9, 2024
    Inventors: Bar Shapira, Ariel Almog, Dotan David Levi, Natan Manevich, Thomas Kernen, Liron Mula
  • Publication number: 20240134731
    Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.
    Type: Application
    Filed: December 5, 2022
    Publication date: April 25, 2024
    Inventors: Natan Manevich, Dotan David Levi, Shay Aisman, Ariel Almog, Ran Avraham Koren
  • Publication number: 20240097876
    Abstract: A communication system includes at least one send queue, containing send queue entries pointing to packets to be transmitted over a network by packet sending circuitry. A clock work queue contains clock queue entries to synchronize sending times of the packets pointed to by the send queue entries. At least one arming queue contains arming queue entries to arm the clock work queue at selected time intervals.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Dotan David Levi, Ariel Shahar, Shahaf Shuler, Ariel Almog, Eitan Hirshberg, Natan Manevich
  • Publication number: 20240089194
    Abstract: A network adapter includes a port and one or more circuits. The port is to send packets to a network in accordance with a Remote Direct Memory Access over Converged Ethernet (RoCE) protocol. The one or more circuits are to decide whether a packet is permitted to undergo Adaptive Routing (AR) in being routed through the network, to mark the packet with an indication of whether the packet is permitted to undergo AR, and to send the marked packet to the network via the port.
    Type: Application
    Filed: November 20, 2022
    Publication date: March 14, 2024
    Inventors: Ariel Almog, Eitan Zahavi, Idan Burstein, Zachy Haramaty, Aviv Barnea
  • Patent number: 11917045
    Abstract: In one embodiment, a communication system includes network devices, each comprising a network interface to receive at least one data stream, a given network device being configured to recover a remote clock from the at least one data stream received by the given network device, a frequency synthesizer to generate a clock signal and output the clock signal to each of the network devices, wherein the given network device is configured to find a clock frequency differential between the clock signal and the recovered remote clock, and provide a control signal to the frequency synthesizer responsively to the clock frequency differential, the control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the clock frequency differential between the clock signal and the recovered remote clock.
    Type: Grant
    Filed: July 24, 2022
    Date of Patent: February 27, 2024
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dotan David Levi, Arnon Sattinger, Natan Manevich, Wojciech Wasko, Ariel Almog, Bar Or Shapira
  • Publication number: 20240031121
    Abstract: In one embodiment, a communication system includes network devices, each comprising a network interface to receive at least one data stream, a given network device being configured to recover a remote clock from the at least one data stream received by the given network device, a frequency synthesizer to generate a clock signal and output the clock signal to each of the network devices, wherein the given network device is configured to find a clock frequency differential between the clock signal and the recovered remote clock, and provide a control signal to the frequency synthesizer responsively to the clock frequency differential, the control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the clock frequency differential between the clock signal and the recovered remote clock.
    Type: Application
    Filed: July 24, 2022
    Publication date: January 25, 2024
    Inventors: Dotan David Levi, Arnon Sattinger, Natan Manevich, Wojciech Wasko, Ariel Almog, Bar Or Shapira
  • Patent number: 11876885
    Abstract: A timing system including timing circuitry which includes an arming queue, a clock work queue, and a clock completion queue. At least the clock work queue is to provide timing information, and the arming queue is to arm the clock work queue. Related apparatus and methods are also provided.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: January 16, 2024
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dotan David Levi, Ariel Shahar, Shahaf Shuler, Ariel Almog, Eitan Hirshberg, Natan Manevich
  • Patent number: 11835999
    Abstract: A system is disclosed that includes two or more network elements, each comprising a Precision Time Protocol (PTP) Hardware Clock (PHC) that is adjustable based, at least in part, on physical layer frequency information.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: December 5, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Bar Shapira, Ariel Almog, Dotan David Levi, Natan Manevich, Thomas Kernen
  • Publication number: 20230370305
    Abstract: In one embodiment, a synchronized communication system includes a plurality of network devices, and clock connections to connect the network devices in a closed loop configuration, wherein the network devices are configured to distribute among the network devices a reference clock time from any selected one of the network devices.
    Type: Application
    Filed: August 11, 2022
    Publication date: November 16, 2023
    Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ariel Almog, Bar Shapira
  • Publication number: 20230367358
    Abstract: In one embodiment, a synchronized communication system includes a first network device and a second network device, wherein the first network device includes a first physical hardware clock, and is configured to recover a reference clock time from packets received from a remote clock, find a clock differential between a clock time output by the first physical hardware clock and the recovered reference clock time, provide a control signal to the second network device responsively to the clock differential, and the second network device includes a second physical hardware clock, and is configured to adjust a clock time output by the second physical hardware clock responsively to the control signal.
    Type: Application
    Filed: July 19, 2022
    Publication date: November 16, 2023
    Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ariel Almog, Bar Shapira
  • Patent number: 11757614
    Abstract: In one embodiment, a processing apparatus includes processing circuitry to process an event, a timestamping unit to generate a timestamp for the event, at least one register to store at least one parameter describing a hardware state of the processing circuitry, and timestamp correction processing circuitry to compute a time value as a correction to the generated timestamp responsively to the at least one parameter.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: September 12, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dotan David Levi, Wojciech Wasko, Natan Manevich, Teferet Geula, Amit Mandelbaum, Ariel Almog
  • Publication number: 20230275906
    Abstract: A method of determining if a virtual machine is executing a network attack may include using a computing device operating a processor: receiving a plurality of jobs from a plurality of virtual machines being executed across time slices on a host computer in a computer network; executing the plurality of jobs using the processor; receiving data from hardware counters of the processor; and based on the data, determining whether or not a virtual machine of the plurality of virtual machines is executing a network attack.
    Type: Application
    Filed: February 28, 2022
    Publication date: August 31, 2023
    Applicant: Mellanox Technologies Ltd.
    Inventors: Ohad ZOHAR, Dotan Finkelshtein, Ariel Almog, Nir Getter, Amit Mandelbaum
  • Publication number: 20230229188
    Abstract: A system is disclosed that includes two or more network elements, each comprising a Precision Time Protocol (PTP) Hardware Clock (PHC) that is adjustable based, at least in part, on physical layer frequency information.
    Type: Application
    Filed: January 18, 2022
    Publication date: July 20, 2023
    Inventors: Bar Shapira, Ariel Almog, Dotan David Levi, Natan Manevich, Thomas Kernen
  • Publication number: 20230231695
    Abstract: In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.
    Type: Application
    Filed: January 20, 2022
    Publication date: July 20, 2023
    Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ariel Almog, Bar Shapira
  • Patent number: 11706014
    Abstract: In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: July 18, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ariel Almog, Bar Shapira
  • Patent number: 11641245
    Abstract: In one embodiment, an event processing system includes a clock configured to provide time values, and event processing circuitry, which is configured to generate a confidence level indicative of a degree of confidence of an accuracy of a timestamp, the timestamp being generated for an event responsively to a time value indicative of when an operation associated with the event occurred.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: May 2, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dotan David Levi, Wojciech Wasko, Natan Manevich, Roee Moyal, Eliel Peretz, Eran Ben Elisha, Ariel Almog, Teferet Geula, Amit Mandelbaum