Patents by Inventor Ariel Almog

Ariel Almog has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220224500
    Abstract: A network device includes one or more ports for connecting to a communication network, packet processing circuitry and clock circuitry. The packet processing circuitry is configured to communicate packets over the communication network via the ports. The clock circuitry includes a hardware clock configured to indicate a network time used for synchronizing network devices in the communication network, and a built-in accuracy test circuit configured to check an accuracy of the hardware clock.
    Type: Application
    Filed: January 14, 2021
    Publication date: July 14, 2022
    Inventors: Liron Mula, Dotan David Levi, Ariel Almog
  • Publication number: 20220191275
    Abstract: A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 16, 2022
    Inventors: Dotan David Levi, Avraham Ganor, Arnon Sattinger, Natan Manevich, Reuven Kogan, Artiom Tsur, Ariel Almog, Bar Shapira
  • Publication number: 20220006606
    Abstract: A timing system including timing circuitry which includes an arming queue, a clock work queue, and a clock completion queue. At least the clock work queue is to provide timing information, and the arming queue is to arm the clock work queue. Related apparatus and methods are also provided.
    Type: Application
    Filed: June 1, 2021
    Publication date: January 6, 2022
    Inventors: Dotan David Levi, Ariel Shahar, Shahaf Shuler, Ariel Almog, Eitan Hirshberg, Natan Manevich
  • Publication number: 20210303385
    Abstract: In one embodiment, a processing device includes a memory, and configured to provide a data dump of the memory, a storage element configured to store a dictionary including interpreter vocabulary to interpret at least some segments of the data dump, and a data dump analysis device including an interface configured to transfer data with the processing device, a dump extraction engine configured to connect with the processing device over the interface, and receive at least one segment of the data dump from the processing device over the interface, and a dump interpretation engine configured to receive at least a subset of the interpreter vocabulary from the dictionary to interpret the received at least one segment, and interpret data of the at least one segment responsively to the received at least subset of the interpreter vocabulary.
    Type: Application
    Filed: January 20, 2021
    Publication date: September 30, 2021
    Inventors: Ariel Almog, Eyal Davidovich, Aviv Shmilovitch
  • Publication number: 20210297151
    Abstract: A network element one or more network ports, network time circuitry and packet processing circuitry. The network ports are configured to communicate with a communication network. The network time circuitry is configured to track a network time defined in the communication network. In some embodiments the packet processing circuitry is configured to receive a definition of one or more timeslots that are synchronized to the network time, and to send outbound packets to the communication network depending on the timeslots. In some embodiments the packet processing circuitry is configured to process inbound. packets, which are received from the communication network, depending on the timeslots.
    Type: Application
    Filed: July 7, 2020
    Publication date: September 23, 2021
    Inventors: Dotan David Levi, Avi Urman, Lior Narkis, Liron Mula, Paraskevas Bakopoulos, Ariel Almog, Roee Moyal, Gal Yefet
  • Publication number: 20210141413
    Abstract: In one embodiment, a network interface card device includes communication interfaces to provide data connection with respective local devices configured to run respective clock synchronization clients, at least one network interface to provide data connection between a packet data network and ones of the local devices, and a hardware clock to maintain a time value, and serve the clock synchronization clients.
    Type: Application
    Filed: February 2, 2020
    Publication date: May 13, 2021
    Inventors: Dotan David Levi, Liron Mula, Ariel Almog, Aviad Raveh, Yuval Itkin
  • Patent number: 10778361
    Abstract: A method including providing a network element including an ingress port, an egress port, and a delay equalizer, providing an equalization message generator, receiving, at the ingress port, a plurality of data packets from multiple sources, each data packet having a source indication and a source-provided time stamp, determining, at the ingress port, a received time stamp for at least some of the received data packets, passing the received data packets, the source-provided time stamps, and the received time stamps to the delay equalizer, the delay equalizer computing, for each source, a delay for synchronizing that source with other sources, the equalization message generator receiving an output, for each source, including the delay for that source, from the delay equalizer and producing a delay message instructing each source regarding the delay for that source, and sending, from the egress port, the delay message to each source. Related apparatus is also provided.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: September 15, 2020
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: Ariel Almog, Thomas Kernen, Dotan David Levi
  • Publication number: 20200287644
    Abstract: A method including providing a network element including an ingress port, an egress port, and a delay equalizer, providing an equalization message generator, receiving, at the ingress port, a plurality of data packets from multiple sources, each data packet having a source indication and a source-provided time stamp, determining, at the ingress port, a received time stamp for at least some of the received data packets, passing the received data packets, the source-provided time stamps, and the received time stamps to the delay equalizer, the delay equalizer computing, for each source, a delay for synchronizing that source with other sources, the equalization message generator receiving an output, for each source, including the delay for that source, from the delay equalizer and producing a delay message instructing each source regarding the delay for that source, and sending, from the egress port, the delay message to each source. Related apparatus is also provided.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 10, 2020
    Inventors: Ariel Almog, Thomas Kernen, Dotan David Levi
  • Publication number: 20200162234
    Abstract: Apparatus including a shared device in communication with a plurality of computing machines external to the shared device, the shared device including at least one PTP domain coefficient storage area, the at least one PTP domain coefficient storage area receiving a PTP coefficient from a computing machine having a PTP client, and providing the PTP coefficient to a computing machine not having a PTP client. Related apparatus and methods are also provided.
    Type: Application
    Filed: November 14, 2019
    Publication date: May 21, 2020
    Inventors: Ariel Almog, Thomas Kernen, Alex Vainman, Nir Nitzani, Dotan David Levi, Ilan Smith, Rafi Wiener
  • Patent number: 10515066
    Abstract: Described embodiments include an apparatus that includes circuitry, configured to facilitate writing to a shared memory, and a processor. The processor is configured to compute a local current-version number by incrementing a shared current-version number that is stored in the shared memory. The processor is further configured to, subsequently to computing the local current-version number, using the circuitry, atomically write at least part of the local current-version number to a portion of the shared memory that is referenced by the local current-version number. The processor is further configured to, subsequently to atomically writing the at least part of the local current-version number, store data in the shared memory in association with the at least part of the local current-version number, and subsequently to storing the data, atomically overwrite the shared current-version number with the local current-version number. Other embodiments are also described.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: December 24, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Guy Shattah, Ariel Almog
  • Publication number: 20190095475
    Abstract: Described embodiments include an apparatus that includes circuitry, configured to facilitate writing to a shared memory, and a processor. The processor is configured to compute a local current-version number by incrementing a shared current-version number that is stored in the shared memory. The processor is further configured to, subsequently to computing the local current-version number, using the circuitry, atomically write at least part of the local current-version number to a portion of the shared memory that is referenced by the local current-version number. The processor is further configured to, subsequently to atomically writing the at least part of the local current-version number, store data in the shared memory in association with the at least part of the local current-version number, and subsequently to storing the data, atomically overwrite the shared current-version number with the local current-version number. Other embodiments are also described.
    Type: Application
    Filed: September 27, 2017
    Publication date: March 28, 2019
    Inventors: Guy Shattah, Ariel Almog
  • Patent number: 9706017
    Abstract: A method for classification includes storing in a TCAM classification rules comprising respective tags, each including an update bit. Data items are classified by extracting a respective key from each data item, appending an update-select bit to construct an extended key, and matching the extended key to one of the tags in the TCAM. In response to an instruction to atomically replace a group of existing rules in the TCAM with new rules, the update bit is unmasked and set to the first bit value in the group of the existing rules. The new rules are stored in the TCAM, with their update bit set to a second bit value. After storing the new rules in the TCAM, the update-select bit in the extended key of the received data items is set to the second bit value.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: July 11, 2017
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: Ariel Almog, Aviv Kfir, David Mozes, Barak Gafni
  • Publication number: 20170094036
    Abstract: A method for classification includes storing in a TCAM classification rules comprising respective tags, each including an update bit. Data items are classified by extracting a respective key from each data item, appending an update-select bit to construct an extended key, and matching the extended key to one of the tags in the TCAM. In response to an instruction to atomically replace a group of existing rules in the TCAM with new rules, the update bit is unmasked and set to the first bit value in the group of the existing rules. The new rules are stored in the TCAM, with their update bit set to a second bit value. After storing the new rules in the TCAM, the update-select bit in the extended key of the received data items is set to the second bit value.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 30, 2017
    Inventors: Ariel Almog, Aviv Kfir, David Mozes, Barak Gafni
  • Patent number: 9197586
    Abstract: Network apparatus includes a plurality of interfaces, which are coupled to a network so as to receive and transmit data packets having respective link-layer headers and network-layer headers. Each link-layer header includes respective source and destination link-layer addresses and a link-layer priority value. Switching and routing logic is configured, responsively to the network-layer headers, to transfer each data packet from a respective ingress interface to a respective egress interface and to modify the source and destination link-layer addresses of the transferred data packet while copying the link-layer priority value from the ingress interface to the egress interface without modification.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: November 24, 2015
    Assignee: MELLANOX TECHNOLOGIES LTD.
    Inventors: Ariel Almog, Gil Bloch
  • Patent number: 8982703
    Abstract: A method for communication in a packet data network including at least first and second subnets interconnected by routers. The method includes defining at least first and second classes of link-layer traffic within the subnets, such that the link-layer traffic in the first class is transmitted among nodes in the network without loss of packets, while at least some of the packets in the second class are dropped in case of network congestion. The routers are configured by transmitting control traffic over the network in the packets of the second class. Data traffic is transmitted between the nodes in the first and second subnets via the configured routers in the packets of the first class.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: March 17, 2015
    Assignee: Mellanox Technologies Ltd.
    Inventors: Ariel Almog, Yaniv Saar, Aviad Raveh, Dror Goldenberg
  • Publication number: 20140169170
    Abstract: Network apparatus includes a plurality of interfaces, which are coupled to a network so as to receive and transmit data packets having respective link-layer headers and network-layer headers. Each link-layer header includes respective source and destination link-layer addresses and a link-layer priority value. Switching and routing logic is configured, responsively to the network-layer headers, to transfer each data packet from a respective ingress interface to a respective egress interface and to modify the source and destination link-layer addresses of the transferred data packet while copying the link-layer priority value from the ingress interface to the egress interface without modification.
    Type: Application
    Filed: January 31, 2013
    Publication date: June 19, 2014
    Applicant: MELLANOX TECHNOLOGIES LTD.
    Inventors: Ariel Almog, Gil Bloch
  • Publication number: 20140169169
    Abstract: A method for communication in a packet data network including at least first and second subnets interconnected by routers. The method includes defining at least first and second classes of link-layer traffic within the subnets, such that the link-layer traffic in the first class is transmitted among nodes in the network without loss of packets, while at least some of the packets in the second class are dropped in case of network congestion. The routers are configured by transmitting control traffic over the network in the packets of the second class. Data traffic is transmitted between the nodes in the first and second subnets via the configured routers in the packets of the first class.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Applicant: MELLANOX TECHNOLOGIES LTD.
    Inventors: Ariel Almog, Yaniv Saar, Aviad Raveh, Dror Goldenberg
  • Patent number: 8457488
    Abstract: A system for serving N optical communication lines by a redundant set of modules in an optical network; where the set of modules comprises N>1 main modules and one backup module, N optical splitters, 2N fiber connections and a control means. In the system, each of the N optical splitters is connected to two different modules of the set by two respective fiber connections out of the 2N connections, while each of the N optical splitters is also coupled to one of the N optical communication lines. The arrangement is such that the control means selectively activates/inactivates any of the fiber connections for respectively enabling/blocking transfer of data there-along; the control means thus ensures that each specific line of the N optical communication lines is always served by either one or another of two different modules.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: June 4, 2013
    Assignee: ECI Telecom Ltd.
    Inventor: Ariel Almog
  • Publication number: 20100316390
    Abstract: A system for serving N optical communication lines by a redundant set of modules in an optical network; where the set of modules comprises N>1 main modules and one backup module, N optical splitters, 2N fiber connections and a control means. In the system, each of the N optical splitters is connected to two different modules of the set by two respective fiber connections out of the 2N connections, while each of the N optical splitters is also coupled to one of the N optical communication lines. The arrangement is such that the control means selectively activates/inactivates any of the fiber connections for respectively enabling/blocking transfer of data there-along; the control means thus ensures that each specific line of the N optical communication lines is always served by either one or another of two different modules.
    Type: Application
    Filed: January 21, 2009
    Publication date: December 16, 2010
    Applicant: ECI Telecom Ltd.
    Inventor: Ariel Almog
  • Publication number: 20040223519
    Abstract: An inverse multiplexing method for transmitting data via multiple data links and a system for implementing same. Efficient utilization of links having disparate data rates is provided by apportioning data units to the links in proportion to their data rates. Rather than perform the apportioning algorithm in real time, the algorithm is executed off-line, and the results recorded as a mapping vector. The mapping vector is used by the transmitter to apportion data units to the links, and by the receiver to re-assemble the data units.
    Type: Application
    Filed: May 5, 2003
    Publication date: November 11, 2004
    Applicant: SPEDIANT SYSTEMS LTD.
    Inventors: Zeev Oster, Ariel Almog