Patents by Inventor Ariel Almog
Ariel Almog has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220360423Abstract: In one embodiment, a processing apparatus includes processing circuitry to process an event, a timestamping unit to generate a timestamp for the event, at least one register to store at least one parameter describing a hardware state of the processing circuitry, and timestamp correction processing circuitry to compute a time value as a correction to the generated timestamp responsively to the at least one parameter.Type: ApplicationFiled: May 10, 2021Publication date: November 10, 2022Inventors: Dotan David Levi, Wojciech Wasko, Natan Manevich, Teferet Geula, Amit Mandelbaum, Ariel Almog
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Publication number: 20220352998Abstract: In one embodiment, an event processing system includes a clock configured to provide time values, and event processing circuitry, which is configured to generate a confidence level indicative of a degree of confidence of an accuracy of a timestamp, the timestamp being generated for an event responsively to a time value indicative of when an operation associated with the event occurred.Type: ApplicationFiled: May 3, 2021Publication date: November 3, 2022Inventors: Dotan David Levi, Wojciech Wasko, Natan Manevich, Roee Moyal, Eliel Peretz, Eran Ben Elisha, Ariel Almog, Teferet Geula, Amit Mandelbaum
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Patent number: 11483127Abstract: Apparatus including a shared device in communication with a plurality of computing machines external to the shared device, the shared device including at least one PTP domain coefficient storage area, the at least one PTP domain coefficient storage area receiving a PTP coefficient from a computing machine having a PTP client, and providing the PTP coefficient to a computing machine not having a PTP client. Related apparatus and methods are also provided.Type: GrantFiled: November 14, 2019Date of Patent: October 25, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ariel Almog, Thomas Kernen, Alex Vainman, Nir Nitzani, Dotan David Levi, Ilan Smith, Rafi Wiener
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Patent number: 11476928Abstract: A network element one or more network ports, network time circuitry and packet processing circuitry. The network ports are configured to communicate with a communication network. The network time circuitry is configured to track a network time defined in the communication network. In some embodiments the packet processing circuitry is configured to receive a definition of one or more timeslots that are synchronized to the network time, and to send outbound packets to the communication network depending on the timeslots. In some embodiments the packet processing circuitry is configured to process inbound packets, which are received from the communication network, depending on the timeslots.Type: GrantFiled: July 7, 2020Date of Patent: October 18, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dotan David Levi, Avi Urman, Lior Narkis, Liron Mula, Paraskevas Bakopoulos, Ariel Almog, Roee Moyal, Gal Yefet
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Publication number: 20220224500Abstract: A network device includes one or more ports for connecting to a communication network, packet processing circuitry and clock circuitry. The packet processing circuitry is configured to communicate packets over the communication network via the ports. The clock circuitry includes a hardware clock configured to indicate a network time used for synchronizing network devices in the communication network, and a built-in accuracy test circuit configured to check an accuracy of the hardware clock.Type: ApplicationFiled: January 14, 2021Publication date: July 14, 2022Inventors: Liron Mula, Dotan David Levi, Ariel Almog
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Publication number: 20220191275Abstract: A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.Type: ApplicationFiled: December 14, 2020Publication date: June 16, 2022Inventors: Dotan David Levi, Avraham Ganor, Arnon Sattinger, Natan Manevich, Reuven Kogan, Artiom Tsur, Ariel Almog, Bar Shapira
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Publication number: 20220006606Abstract: A timing system including timing circuitry which includes an arming queue, a clock work queue, and a clock completion queue. At least the clock work queue is to provide timing information, and the arming queue is to arm the clock work queue. Related apparatus and methods are also provided.Type: ApplicationFiled: June 1, 2021Publication date: January 6, 2022Inventors: Dotan David Levi, Ariel Shahar, Shahaf Shuler, Ariel Almog, Eitan Hirshberg, Natan Manevich
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Publication number: 20210303385Abstract: In one embodiment, a processing device includes a memory, and configured to provide a data dump of the memory, a storage element configured to store a dictionary including interpreter vocabulary to interpret at least some segments of the data dump, and a data dump analysis device including an interface configured to transfer data with the processing device, a dump extraction engine configured to connect with the processing device over the interface, and receive at least one segment of the data dump from the processing device over the interface, and a dump interpretation engine configured to receive at least a subset of the interpreter vocabulary from the dictionary to interpret the received at least one segment, and interpret data of the at least one segment responsively to the received at least subset of the interpreter vocabulary.Type: ApplicationFiled: January 20, 2021Publication date: September 30, 2021Inventors: Ariel Almog, Eyal Davidovich, Aviv Shmilovitch
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Publication number: 20210297151Abstract: A network element one or more network ports, network time circuitry and packet processing circuitry. The network ports are configured to communicate with a communication network. The network time circuitry is configured to track a network time defined in the communication network. In some embodiments the packet processing circuitry is configured to receive a definition of one or more timeslots that are synchronized to the network time, and to send outbound packets to the communication network depending on the timeslots. In some embodiments the packet processing circuitry is configured to process inbound. packets, which are received from the communication network, depending on the timeslots.Type: ApplicationFiled: July 7, 2020Publication date: September 23, 2021Inventors: Dotan David Levi, Avi Urman, Lior Narkis, Liron Mula, Paraskevas Bakopoulos, Ariel Almog, Roee Moyal, Gal Yefet
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Publication number: 20210141413Abstract: In one embodiment, a network interface card device includes communication interfaces to provide data connection with respective local devices configured to run respective clock synchronization clients, at least one network interface to provide data connection between a packet data network and ones of the local devices, and a hardware clock to maintain a time value, and serve the clock synchronization clients.Type: ApplicationFiled: February 2, 2020Publication date: May 13, 2021Inventors: Dotan David Levi, Liron Mula, Ariel Almog, Aviad Raveh, Yuval Itkin
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Patent number: 10778361Abstract: A method including providing a network element including an ingress port, an egress port, and a delay equalizer, providing an equalization message generator, receiving, at the ingress port, a plurality of data packets from multiple sources, each data packet having a source indication and a source-provided time stamp, determining, at the ingress port, a received time stamp for at least some of the received data packets, passing the received data packets, the source-provided time stamps, and the received time stamps to the delay equalizer, the delay equalizer computing, for each source, a delay for synchronizing that source with other sources, the equalization message generator receiving an output, for each source, including the delay for that source, from the delay equalizer and producing a delay message instructing each source regarding the delay for that source, and sending, from the egress port, the delay message to each source. Related apparatus is also provided.Type: GrantFiled: March 4, 2019Date of Patent: September 15, 2020Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: Ariel Almog, Thomas Kernen, Dotan David Levi
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Publication number: 20200287644Abstract: A method including providing a network element including an ingress port, an egress port, and a delay equalizer, providing an equalization message generator, receiving, at the ingress port, a plurality of data packets from multiple sources, each data packet having a source indication and a source-provided time stamp, determining, at the ingress port, a received time stamp for at least some of the received data packets, passing the received data packets, the source-provided time stamps, and the received time stamps to the delay equalizer, the delay equalizer computing, for each source, a delay for synchronizing that source with other sources, the equalization message generator receiving an output, for each source, including the delay for that source, from the delay equalizer and producing a delay message instructing each source regarding the delay for that source, and sending, from the egress port, the delay message to each source. Related apparatus is also provided.Type: ApplicationFiled: March 4, 2019Publication date: September 10, 2020Inventors: Ariel Almog, Thomas Kernen, Dotan David Levi
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Publication number: 20200162234Abstract: Apparatus including a shared device in communication with a plurality of computing machines external to the shared device, the shared device including at least one PTP domain coefficient storage area, the at least one PTP domain coefficient storage area receiving a PTP coefficient from a computing machine having a PTP client, and providing the PTP coefficient to a computing machine not having a PTP client. Related apparatus and methods are also provided.Type: ApplicationFiled: November 14, 2019Publication date: May 21, 2020Inventors: Ariel Almog, Thomas Kernen, Alex Vainman, Nir Nitzani, Dotan David Levi, Ilan Smith, Rafi Wiener
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Patent number: 10515066Abstract: Described embodiments include an apparatus that includes circuitry, configured to facilitate writing to a shared memory, and a processor. The processor is configured to compute a local current-version number by incrementing a shared current-version number that is stored in the shared memory. The processor is further configured to, subsequently to computing the local current-version number, using the circuitry, atomically write at least part of the local current-version number to a portion of the shared memory that is referenced by the local current-version number. The processor is further configured to, subsequently to atomically writing the at least part of the local current-version number, store data in the shared memory in association with the at least part of the local current-version number, and subsequently to storing the data, atomically overwrite the shared current-version number with the local current-version number. Other embodiments are also described.Type: GrantFiled: September 27, 2017Date of Patent: December 24, 2019Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Guy Shattah, Ariel Almog
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Publication number: 20190095475Abstract: Described embodiments include an apparatus that includes circuitry, configured to facilitate writing to a shared memory, and a processor. The processor is configured to compute a local current-version number by incrementing a shared current-version number that is stored in the shared memory. The processor is further configured to, subsequently to computing the local current-version number, using the circuitry, atomically write at least part of the local current-version number to a portion of the shared memory that is referenced by the local current-version number. The processor is further configured to, subsequently to atomically writing the at least part of the local current-version number, store data in the shared memory in association with the at least part of the local current-version number, and subsequently to storing the data, atomically overwrite the shared current-version number with the local current-version number. Other embodiments are also described.Type: ApplicationFiled: September 27, 2017Publication date: March 28, 2019Inventors: Guy Shattah, Ariel Almog
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Patent number: 9706017Abstract: A method for classification includes storing in a TCAM classification rules comprising respective tags, each including an update bit. Data items are classified by extracting a respective key from each data item, appending an update-select bit to construct an extended key, and matching the extended key to one of the tags in the TCAM. In response to an instruction to atomically replace a group of existing rules in the TCAM with new rules, the update bit is unmasked and set to the first bit value in the group of the existing rules. The new rules are stored in the TCAM, with their update bit set to a second bit value. After storing the new rules in the TCAM, the update-select bit in the extended key of the received data items is set to the second bit value.Type: GrantFiled: September 29, 2015Date of Patent: July 11, 2017Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: Ariel Almog, Aviv Kfir, David Mozes, Barak Gafni
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Publication number: 20170094036Abstract: A method for classification includes storing in a TCAM classification rules comprising respective tags, each including an update bit. Data items are classified by extracting a respective key from each data item, appending an update-select bit to construct an extended key, and matching the extended key to one of the tags in the TCAM. In response to an instruction to atomically replace a group of existing rules in the TCAM with new rules, the update bit is unmasked and set to the first bit value in the group of the existing rules. The new rules are stored in the TCAM, with their update bit set to a second bit value. After storing the new rules in the TCAM, the update-select bit in the extended key of the received data items is set to the second bit value.Type: ApplicationFiled: September 29, 2015Publication date: March 30, 2017Inventors: Ariel Almog, Aviv Kfir, David Mozes, Barak Gafni
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Patent number: 9197586Abstract: Network apparatus includes a plurality of interfaces, which are coupled to a network so as to receive and transmit data packets having respective link-layer headers and network-layer headers. Each link-layer header includes respective source and destination link-layer addresses and a link-layer priority value. Switching and routing logic is configured, responsively to the network-layer headers, to transfer each data packet from a respective ingress interface to a respective egress interface and to modify the source and destination link-layer addresses of the transferred data packet while copying the link-layer priority value from the ingress interface to the egress interface without modification.Type: GrantFiled: January 31, 2013Date of Patent: November 24, 2015Assignee: MELLANOX TECHNOLOGIES LTD.Inventors: Ariel Almog, Gil Bloch
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Patent number: 8982703Abstract: A method for communication in a packet data network including at least first and second subnets interconnected by routers. The method includes defining at least first and second classes of link-layer traffic within the subnets, such that the link-layer traffic in the first class is transmitted among nodes in the network without loss of packets, while at least some of the packets in the second class are dropped in case of network congestion. The routers are configured by transmitting control traffic over the network in the packets of the second class. Data traffic is transmitted between the nodes in the first and second subnets via the configured routers in the packets of the first class.Type: GrantFiled: December 18, 2012Date of Patent: March 17, 2015Assignee: Mellanox Technologies Ltd.Inventors: Ariel Almog, Yaniv Saar, Aviad Raveh, Dror Goldenberg
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Publication number: 20140169170Abstract: Network apparatus includes a plurality of interfaces, which are coupled to a network so as to receive and transmit data packets having respective link-layer headers and network-layer headers. Each link-layer header includes respective source and destination link-layer addresses and a link-layer priority value. Switching and routing logic is configured, responsively to the network-layer headers, to transfer each data packet from a respective ingress interface to a respective egress interface and to modify the source and destination link-layer addresses of the transferred data packet while copying the link-layer priority value from the ingress interface to the egress interface without modification.Type: ApplicationFiled: January 31, 2013Publication date: June 19, 2014Applicant: MELLANOX TECHNOLOGIES LTD.Inventors: Ariel Almog, Gil Bloch