Patents by Inventor Ariel Hendel
Ariel Hendel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250219957Abstract: An adaptive generic receive offload (A-GRO) system and method are disclosed. In some embodiments, the system comprises a host including a host protocol stack and a host memory, and a network interface card that is communicatively connectable to the host. The A-GRO system is configured to: receive a packet from a network, parse the packet to a header and a payload, classify and map the packet into a particular flow based on contexts associated with a plurality of flows and the header, and move the header and the payload to separate queues associated with the particular flow in the host memory, without holding and stalling the packet in hardware of the NIC. By maintain packet coherence information including header chains, the A-GRO allows the host to skip processing the packets between the first and last headers in a GRO aggregation. The A-GRO system also improves mis-ordering packet handling.Type: ApplicationFiled: March 14, 2025Publication date: July 3, 2025Inventors: Shrijeet Mukherjee, Carlo Contavalli, Shimon Muller, Ariel Hendel, Gurjeet Singh, Rochan Sankar
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Publication number: 20250211539Abstract: An adaptive generic receive offload (A-GRO) system and method are disclosed. In some embodiments, the system comprises a host including a host protocol stack and a host memory, and a network interface card that is communicatively connectable to the host. The A-GRO system is configured to: receive a packet from a network, parse the packet to a header and a payload, classify and map the packet into a particular flow based on contexts associated with a plurality of flows and the header, and move the header and the payload to separate queues associated with the particular flow in the host memory, without holding and stalling the packet in hardware of the NIC. By maintain packet coherence information including header chains, the A-GRO allows the host to skip processing the packets between the first and last headers in a GRO aggregation. The A-GRO system also improves mis-ordering packet handling.Type: ApplicationFiled: March 13, 2025Publication date: June 26, 2025Inventors: Shrijeet Mukherjee, Carlo Contavalli, Shimon Muller, Ariel Hendel, Gurjeet Singh, Rochan Sankar
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Patent number: 12255826Abstract: An adaptive generic receive offload (A-GRO) system and method are disclosed. In some embodiments, the system comprises a host including a host protocol stack and a host memory, and a network interface card that is communicatively connectable to the host. The A-GRO system is configured to: receive a packet from a network, parse the packet to a header and a payload, classify and map the packet into a particular flow based on contexts associated with a plurality of flows and the header, and move the header and the payload to separate queues associated with the particular flow in the host memory, without holding and stalling the packet in hardware of the NIC. By maintain packet coherence information including header chains, the A-GRO allows the host to skip processing the packets between the first and last headers in a GRO aggregation. The A-GRO system also improves mis-ordering packet handling.Type: GrantFiled: January 12, 2023Date of Patent: March 18, 2025Assignee: Enfabrica CorporationInventors: Shrijeet Mukherjee, Carlo Contavalli, Shimon Muller, Ariel Hendel, Gurjeet Singh, Rochan Sankar
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Patent number: 12244494Abstract: A server fabric adapter (SFA) communication system is disclosed. In some embodiments, the SFA communication system comprises an SFA communicatively coupled to a plurality of controlling hosts, a plurality of endpoints, and a plurality of network ports. The SFA is configured to receive a network packet from a network port of the plurality of network ports; separate the network packet into different portions, each portion including a header or a payload; map each portion of the network packet to: (i) a controlling host of the plurality controlling hosts, the controlling host being designated as a destination controlling host, or (ii) an endpoint of the plurality of endpoints, the endpoint being designated as a destination endpoint; and forward a respective portion of the network packet to the destination controlling host or the destination endpoint.Type: GrantFiled: July 19, 2024Date of Patent: March 4, 2025Assignee: Enfabrica CorporationInventors: Rochan Sankar, Shrijeet Mukherjee, Ariel Hendel, Carlo Contavalli, Shimon Muller
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Publication number: 20250047621Abstract: In an aspect, a system for an optimally balanced networked system is disclosed. The system includes a fabric adapter communication system communicatively coupled to a plurality of network ports and a plurality of controlling hosts. The fabric adapter communication system is configured to receive a network packet from, or transmit a network packet to, a network port of the plurality of network ports. The fabric adapter communication system is configured to separate the network packet into different portions, each portion including a header or a payload. The fabric adapter communication system is configured to forward the headers of the different portions to one or more controlling hosts. The fabric adapter communication system is configured to forward multiple payloads of the different portions in parallel through a bundled interface to multiple memory buffers of a global memory pool based on one or more scatter gather lists (SGLs).Type: ApplicationFiled: June 18, 2024Publication date: February 6, 2025Inventors: Rochan Sankar, Shrijeet Mukherjee, Ariel Hendel, Carlo Contavalli, Shimon Muller
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Publication number: 20240372805Abstract: A server fabric adapter (SFA) communication system is disclosed. In some embodiments, the SFA communication system comprises an SFA communicatively coupled to a plurality of controlling hosts, a plurality of endpoints, and a plurality of network ports. The SFA is configured to receive a network packet from a network port of the plurality of network ports; separate the network packet into different portions, each portion including a header or a payload; map each portion of the network packet to: (i) a controlling host of the plurality controlling hosts, the controlling host being designated as a destination controlling host, or (ii) an endpoint of the plurality of endpoints, the endpoint being designated as a destination endpoint; and forward a respective portion of the network packet to the destination controlling host or the destination endpoint.Type: ApplicationFiled: July 19, 2024Publication date: November 7, 2024Inventors: Rochan Sankar, Shrijeet Mukherjee, Ariel Hendel, Carlo Contavalli, Shimon Muller
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Patent number: 12120021Abstract: A server fabric adapter (SFA) communication system is disclosed. In some embodiments, the SFA communication system comprises an SFA communicatively coupled to a plurality of controlling hosts, a plurality of endpoints, and a plurality of network ports. The SFA is configured to receive a network packet from a network port of the plurality of network ports; separate the network packet into different portions, each portion including a header or a payload; map each portion of the network packet to: (i) a controlling host of the plurality controlling hosts, the controlling host being designated as a destination controlling host, or (ii) an endpoint of the plurality of endpoints, the endpoint being designated as a destination endpoint; and forward a respective portion of the network packet to the destination controlling host or the destination endpoint.Type: GrantFiled: January 6, 2022Date of Patent: October 15, 2024Assignee: Enfabrica CorporationInventors: Rochan Sankar, Shrijeet Mukherjee, Ariel Hendel, Carlo Contavalli, Shimon Muller
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Publication number: 20240330221Abstract: A multi-plane, multi-protocol memory switch system is disclosed. In some embodiments, a memory switch includes a plurality of switch ports, the memory switch connectable to one or more root complex (RC) devices through one or more respective switch ports of the plurality of switch ports, and the memory switch connectable to a set of endpoints through a set of other switch ports of the plurality of switch ports, wherein the set includes zero or multiple endpoints; a cacheline exchange engine configured to provide a data-exchange path between two endpoints and to map an address space of one endpoint to an address space of another endpoint; and a bulk data transfer engine configured to facilitate data-exchange between two endpoints as a source-destination data stream, one endpoint being designated a source address and another endpoint being designated a destination address.Type: ApplicationFiled: June 13, 2024Publication date: October 3, 2024Inventors: Thomas Norrie, Shrijeet Mukherjee, John Greth, Rochan Sankar, Shimon Muller, Ariel Hendel, Gurjeet Singh
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Publication number: 20240264964Abstract: A multi-plane, multi-protocol memory switch system is disclosed. In some embodiments, a memory switch includes a plurality of switch ports, the memory switch connectable to one or more root complex (RC) devices through one or more respective switch ports of the plurality of switch ports, and the memory switch connectable to a set of endpoints through a set of other switch ports of the plurality of switch ports, wherein the set includes zero or multiple endpoints; a cacheline exchange engine configured to provide a data-exchange path between two endpoints and to map an address space of one endpoint to an address space of another endpoint; and a bulk data transfer engine configured to facilitate data-exchange between two endpoints as a source-destination data stream, one endpoint being designated a source address and another endpoint being designated a destination address.Type: ApplicationFiled: April 18, 2024Publication date: August 8, 2024Inventors: Thomas Norrie, Shrijeet Mukherjee, John Greth, Rochan Sankar, Shimon Muller, Ariel Hendel, Gurjeet Singh
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Publication number: 20240244005Abstract: An adaptive generic receive offload (A-GRO) system and method are disclosed. In some embodiments, the system comprises a host including a host protocol stack and a host memory, and a network interface card that is communicatively connectable to the host. The A-GRO system is configured to: receive a packet from a network, parse the packet to a header and a payload, classify and map the packet into a particular flow based on contexts associated with a plurality of flows and the header, and move the header and the payload to separate queues associated with the particular flow in the host memory, without holding and stalling the packet in hardware of the NIC. By maintain packet coherence information including header chains, the A-GRO allows the host to skip processing the packets between the first and last headers in a GRO aggregation. The A-GRO system also improves mis-ordering packet handling.Type: ApplicationFiled: January 12, 2023Publication date: July 18, 2024Inventors: Shrijeet Mukherjee, Carlo Contavalli, Shimon Muller, Ariel Hendel, Gurjeet Singh, Rochan Sankar
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Patent number: 11995017Abstract: A multi-plane, multi-protocol memory switch system is disclosed. In some embodiments, a memory switch includes a plurality of switch ports, the memory switch connectable to one or more root complex (RC) devices through one or more respective switch ports of the plurality of switch ports, and the memory switch connectable to a set of endpoints through a set of other switch ports of the plurality of switch ports, wherein the set includes zero or multiple endpoints; a cacheline exchange engine configured to provide a data-exchange path between two endpoints and to map an address space of one endpoint to an address space of another endpoint; and a bulk data transfer engine configured to facilitate data-exchange between two endpoints as a source-destination data stream, one endpoint being designated a source address and another endpoint being designated a destination address.Type: GrantFiled: June 8, 2022Date of Patent: May 28, 2024Assignee: Enfabrica CorporationInventors: Thomas Norrie, Shrijeet Mukherjee, John Greth, Rochan Sankar, Shimon Muller, Ariel Hendel, Gurjeet Singh
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Publication number: 20230059755Abstract: A system for congestion control using a flow level transmit mechanism is disclosed. In some embodiments, the system comprises a source SFA and a receive SFA. The source SFA is configured to detect and classify a congestion notification packet (CNP) generated based on congestion in a network; select a receive block from a plurality of receive blocks based on the CNP; forward the CNP to a dedicated congestion notification queue of the receive block; identify a transmit queue from a plurality of transmit blocks based on processing the congestion notification queue, wherein the transmit queue originated a particular transmit flow causing the congestion; and stop the transmit queue.Type: ApplicationFiled: August 11, 2022Publication date: February 23, 2023Inventors: Shrijeet Mukherjee, Shimon Muller, Carlo Contavalli, Gurjeet Singh, Ariel Hendel, Rochan Sankar
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Publication number: 20220398207Abstract: A multi-plane, multi-protocol memory switch system is disclosed. In some embodiments, a memory switch includes a plurality of switch ports, the memory switch connectable to one or more root complex (RC) devices through one or more respective switch ports of the plurality of switch ports, and the memory switch connectable to a set of endpoints through a set of other switch ports of the plurality of switch ports, wherein the set includes zero or multiple endpoints; a cacheline exchange engine configured to provide a data-exchange path between two endpoints and to map an address space of one endpoint to an address space of another endpoint; and a bulk data transfer engine configured to facilitate data-exchange between two endpoints as a source-destination data stream, one endpoint being designated a source address and another endpoint being designated a destination address.Type: ApplicationFiled: June 8, 2022Publication date: December 15, 2022Inventors: Thomas Norrie, Shrijeet Mukherjee, John Greth, Rochan Sankar, Shimon Muller, Ariel Hendel, Gurjeet Singh
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Publication number: 20220217085Abstract: A server fabric adapter (SFA) communication system is disclosed. In some embodiments, the SFA communication system comprises an SFA communicatively coupled to a plurality of controlling hosts, a plurality of endpoints, and a plurality of network ports. The SFA is configured to receive a network packet from a network port of the plurality of network ports; separate the network packet into different portions, each portion including a header or a payload; map each portion of the network packet to: (i) a controlling host of the plurality controlling hosts, the controlling host being designated as a destination controlling host, or (ii) an endpoint of the plurality of endpoints, the endpoint being designated as a destination endpoint; and forward a respective portion of the network packet to the destination controlling host or the destination endpoint.Type: ApplicationFiled: January 6, 2022Publication date: July 7, 2022Inventors: Rochan Sankar, Shrijeet Mukherjee, Ariel Hendel, Carlo Contavalli, Shimon Muller
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Patent number: 10708357Abstract: A network-displaced direct storage architecture transports storage commands over a network interface. In one implementation, the architecture maps, at hosts, block storage commands to remote direct memory access operations (e.g., over converged Ethernet). The mapped operations are communicated across the network to a network storage appliance. At the network storage appliance, network termination receives the mapped commands, extracts the operation and data, and passes the operation and data to a storage device that implements the operation on a memory.Type: GrantFiled: March 30, 2018Date of Patent: July 7, 2020Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Ariel Hendel, Karagada Ramarao Kishore
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Patent number: 10341384Abstract: A network function virtualization security and trust system includes a network device that operates as a virtualized network device with virtualized services provided on the network device by network nodes included in the system. Security and trust within the system can include hardware authentication of the network nodes and the network device to obtain a level of security of the hardware provisioning the operation of the virtualized services. Security and trust can also include authentication of the services being used on the virtualized network device. Services authentication can be based on monitoring and analysis of the cooperative operation of the services in the virtualized network device. The virtualized services can be dynamically changed, added or stopped. Hardware authentication and dynamic services authentication in accordance with changes in the virtualized services can dynamically maintain a level of security across the devices and the virtualized services.Type: GrantFiled: August 4, 2015Date of Patent: July 2, 2019Assignee: Avago Technologies International Sales Pte. LimitedInventors: Nicholas Ilyadis, Xuemin Chen, Philippe Klein, Ariel Hendel, Kumaran David Siva
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Patent number: 10205660Abstract: The present disclosure describes a networking switch of a network and method for operating the networking switch. The networking switch communicates within the network using datagrams, such as packets and/or frames. The frames include packets of a first communication protocol or layer having headers of the first communication protocol or layer. In some situations, the packets of the first communication protocol or layer are embedded with packets of a second communication protocol or layer. Often times, one or more fields of headers of the first communication protocol or layer convey substantially similar or redundant information, such as routing information to provide an example, as one or more fields of headers of the second communication protocol or layer.Type: GrantFiled: June 3, 2016Date of Patent: February 12, 2019Assignee: Avago Technologies International Sales Pte. LimitedInventors: Ian Bruce Bernard Cox, Ariel Hendel
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Patent number: 10164870Abstract: A system, method and a computer readable medium for processing packets transmitted using relaxed order in an ordered multi-path network are provided. Packets associated with a data flow from the ordered multi-path network are received out of order. The received packets are reassembled into a sequential order, without gaps, prior to being delivered to a protocol stock for sequential processing.Type: GrantFiled: June 28, 2013Date of Patent: December 25, 2018Assignee: Avago Technologies International Sales Pte. LimitedInventors: Ariel Hendel, Mohan Kalkunte
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Publication number: 20180227365Abstract: A network-displaced direct storage architecture transports storage commands over a network interface. In one implementation, the architecture maps, at hosts, block storage commands to remote direct memory access operations (e.g., over converged Ethernet). The mapped operations are communicated across the network to a network storage appliance. At the network storage appliance, network termination receives the mapped commands, extracts the operation and data, and passes the operation and data to a storage device that implements the operation on a memory.Type: ApplicationFiled: March 30, 2018Publication date: August 9, 2018Applicant: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Ariel HENDEL, Karagada Ramarao Kishore
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Patent number: 9967340Abstract: A network-displaced direct storage architecture transports storage commands over a network interface. In one implementation, the architecture maps, at hosts, block storage commands to remote direct memory access operations (e.g., over converged Ethernet). The mapped operations are communicated across the network to a network storage appliance. At the network storage appliance, network termination receives the mapped commands, extracts the operation and data, and passes the operation and data to a storage device that implements the operation on a memory.Type: GrantFiled: April 9, 2014Date of Patent: May 8, 2018Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Ariel Hendel, Karagada Ramarao Kishore