Abstract: Optimizing the time that a link is active in a data storage device is desirable. Changing the way the device processes commands will minimize the link uptime and maximize the time that the link can remain in a low power mode. The data storage device will control the command arbitration from the host to aggregate together command chunks as large as possible, such that will extend the link down durations, and won't need to wake the link up occasionally. In another approach the execution of commands from internal buffers of the host will be prioritized according to command-batch completion criteria, and not based on minimizing the latency of a single command.

Abstract: A data storage device has an inference engine that can infer a read threshold based on a non-linear function of inputs that reflect current memory and data conditions. The read threshold can be used in reading a wordline in the memory. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and also improve latency, throughput, power consumption, and quality of service.

Abstract: Data storage devices configured to exploit generative-adversarial-networks (GANs). The GANs include super-resolution GANs (SRGANS). In some examples, a GAN-based decoding reconstruction procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated.

Abstract: Methods and apparatus for energy management in data storage devices are provided. One such data storage device (DSD) includes a non-volatile memory (NVM), a set of hardware processing engines, and a power sensor to detect a total power consumption of the set of hardware processing engines. A processor is configured to determine an energy-per-processing event value for each of the set of processing engines based on total power consumption measurements and processing event duration values, then control energy delivery to the processing engines based on the energy-per-processing event values in accordance with an energy budget. In some examples, the DSD employs a least-squares procedure to estimate power-per-processing event values so the values can be determined without needing to measure individual power consumption of the processing engines. The power-per-processing event values are converted to energy-per-processing event values based on corresponding processing event durations.

Abstract: Methods and apparatus for power management in data storage devices are provided wherein conformal prediction is employed to determine correction terms for applying to power-per-processing event (P/PE) values. One such data storage device includes a non-volatile memory (NVM), a set of hardware processing engines, and a power sensor to detect a total power consumption of the set of hardware processing engines. A processor is configured to determine a P/PE value for each of the set of processing engines based on total power consumption measurements using a least squares procedure. A conformalization procedure is applied to sequences of P/PE values to calibrate the P/PE values by determining correction terms for applying to the P/PE values to provide guaranteed power prediction intervals. Delivery of power to the processing engines is then controlled based on the corrected P/PE event values in accordance with a power budget. On-line and off-line examples are provided.

Abstract: The present disclosure generally relates to utilizing improved DL training models stored in non-volatile memory to optimize data transfer and storage. The proposed system would identify workloads of DNN training and occasionally check the difference rate between successive data transfers (representing successive training iterations of the model). Comparing the difference rate to given thresholds could indicate “recommendation-system” typical use case. In such a case the NAND operating system would apply systematic compression of the data by saving only the changed parameters between successive iteration cycles (“batches”). The host may indicate the checkpoint storage configuration of the training model (every iteration, every several iterations etc. . . . ) and other elements. The system may be efficiently utilized combining the NAND based DNN training interface, adding the checkpoint configuration information to the dedicated interface.

Abstract: Rather than using low power mode since there is no indication of a sleep mode type to the data storage device, the sleep mode type is inferred by the data storage device, or supplied by the host. In so doing, the sleep type communication is improved. After the system returns power to the data storage device, there may be a read workload, depending on the sleep type. The workload is characterized by a low-queue depth (QD) sequential read from a specific area of the storage medium that was written to just prior to shut down. In response to inference or host cue, the data storage device will modify an operation so that data storage device is optimized to the sleep mode type, resulting in improved performance and power consumption.

Abstract: More efficient memory device usage is possible by altering the memory device management. For example, when the full storage capacity of the memory device will not be used, certain portions of the memory device can be shut off and then turned on when the storage capacity is needed. When less capacity is needed, data can be consolidated and certain portions of the memory device can be shut off. Additionally, rather than operating in multilevel cell (MLC) memory, the memory device can start in single level cell (SLC) memory and transition to MLC memory over time. If there is a determination that less memory is needed, the memory device can transition from MLC memory to SLC memory. In so doing, the storage capacity of the memory device is more appropriately utilized.

Abstract: The present disclosure generally relates to improving data transfer in a data storage device. In double data rate (DDR) systems that include a data bus inversion (DBI) functionality, bit flip events can be more prevalent. To mitigate the effect of enhanced erroneous bit flip rate related to DBI bit flip events, the DBI bit can stay static for a predetermined number of consecutive clock cycles, the error correction module can be informed of reduced reliability due to active DBI bit events, the DBI bit can be set to 0, or combinations thereof. Setting the DBI bit to 0 effectively cancels DBI functionality. Informing the error correction module permits a more robust error correction to occur. Forcing the DBI bit to remain static reduces the probability of an unrecognized bit flip event of a full byte. In so doing, data transfer reliability is improved when using DBI functionality.

Abstract: Systems, methods, and data storage devices for secured failover access through data storage device side channels are described. Storage devices may include a storage interface and one or more side channels, such as control bus and debug bus interfaces. The different interfaces may use different interface protocols and physical interface connections configured for different types of commands to the data storage device. When a failure of the storage interface occurs, the data storage device may receive a failover message through one or more side channels to reconfigure the side channel interface to receive, execute, and return a response for host storage commands targeting host data on the storage medium.

Abstract: Aspects of the present disclosure generally relate to data storage devices, systems, and related methods that group commands of doorbell transactions from host devices into a plurality of groupings. A controller of a data storage device is configured to receive a plurality of submission doorbell transactions comprising a plurality of commands from a host device. The controller is configured to group the plurality of commands of the plurality of submission doorbell transactions into a plurality of groupings having a grouping order. Each grouping of the plurality of groupings corresponds to a single doorbell transaction of the plurality of submission doorbell transactions. The controller is configured to send one or more completion doorbell transactions to the host device. Each completion doorbell transaction of the one or more completion doorbell transactions identifies a completed grouping of the plurality of groupings.

Abstract: In a storage system having a plurality of solid state drives (SSDs), the performance of propagating data from a primary device to each secondary device may be improved using a dedicated high speed data channel in which data and commands associated with the data is sent from an upstream SSD to a downstream SSD. The data is also sent to the downstream SSD after a minimum amount of data has been programmed to the upstream SSD. The downstream SSD begins programming the data to its own memory device after receiving the data. The programming of data to each SSD of the storage system may be in parallel and at least partially concurrent with each other. Data, commands, and control messages may be sent an upstream SSD via a serial bus or a universal asynchronous receiver-transmitter channel, such that the downstream data paths and the upstream data paths are distinct.

Abstract: A data storage device with partial speed changes to improve in-order data transfer. Rather than determining an ECC decoder on a first available decoder basis, the ECC decoder may be based on the ECC decoder level. A memory device will have at least one FMU that has a syndrome weight (SW). The disclosure proposes assigning FMU's based on the SW rate. At the time the command is read, the data storage device determines which level of decoder will be assigned to the FMU. The determination will then be checked according to different system environment parameters to maintain performance or reduce power consumption. The arrangement allows a more flexible system design that can adapt according to the current system status.

Abstract: Optimizing the time that a link is active in a data storage device is desirable. Changing the way the device processes commands will minimize the link uptime and maximize the time that the link can remain in a low power mode. The data storage device will control the command arbitration from the host to aggregate together command chunks as large as possible, such that will extend the link down durations, and won't need to wake the link up occasionally. In another approach the execution of commands from internal buffers of the host will be prioritized according to command-batch completion criteria, and not based on minimizing the latency of a single command.

Abstract: A data storage device and method for device-initiated hibernation are provided. In one embodiment, the data storage device comprises a non-volatile memory and a controller. The controller is configured to: receive, from a host during a set-up phase of a hibernation process, a plurality of write commands with a current state of a volatile memory in the host; store the plurality of write commands in a queue, wherein the plurality of write commands are not executed during the set-up phase of the hibernation process; receive a trigger from the host to perform an execution phase of the hibernation process; and in response to receiving the trigger, execute the plurality of write commands to store the current state of the host's volatile memory in the non-volatile memory of the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: The present disclosure generally relates to host memory buffer (HMB) cache management in DRAM-less SSDs. HMB is transient memory and may not always be available. For example, when the link between the data storage device and the host device is not active, the data storage device can't access the HMB. Placing an HMB log in the HMB controller that is disposed in the data storage device provides access to data that would otherwise be inaccessible in the HMB. The HMB log contains any deltas that have occurred since either the last copying to an HMB cache in the memory device or any delta that have occurred since the link became inactive. The HMB cache mirrors the HMB. In so doing, the data of the HMB is available to the data storage device not only when the link is active, but also when the link is not active.

Abstract: Data storage devices configured to exploit generative-adversarial-networks (GANs) are described herein, including super-resolution GANs (SRGANs). In some examples, a GAN-based decoding (reconstruction) procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure to permit a reduction in the number of parity bits used while storing the data. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated. System and method examples are provided.

Abstract: Data storage devices configured to exploit generative-adversarial-networks (GANs) are described herein, including super-resolution GANs (SRGANs). In some examples, a GAN-based decoding (reconstruction) procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure to permit a reduction in the number of parity bits used while storing the data. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of image data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated.

Abstract: Data storage devices configured to exploit generative-adversarial-networks (GANs) are described herein, including super-resolution GANs (SRGANs). In some examples, a GAN-based decoding (reconstruction) procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure to permit a reduction in the number of parity bits used while storing the data. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated. System and method examples are provided.

Abstract: The present disclosure generally relates to improving adaptive tuning of different clock rates of a memory device. Rather than clock rates only being determined off of one parameter such as workload, the clock rates now will be determined using multiple parameters. The tuning may be based on system parameters to allow the system to withstand challenges that arise during the operation. The clock frequency table is maintained in the device controller. The table holds the clock frequency of each component. The disclosure proposes modifying the table according to different system environment parameters to maintain performance or reduce power consumption. Adaptive tuning allows a more flexible system design that can adapt according to the current system status. Adaptive tuning also reduces peak power consumption, improves performance, and better quality of service (QoS) compatibility characteristics.