Patents by Inventor Ariel Navon

Ariel Navon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220245242
    Abstract: An apparatus, system, and method for detecting compromised firmware in a non-volatile storage device. A control bus of a non-volatile storage device is monitored. The non-volatile storage device includes a processor and electronic components coupled to the control bus. Signal traffic on the control bus is analyzed for events and/or triggers related to storage operations initiated on the control bus by the processor. Storage operations include one or more commands directed to at least one of the electronic components. If the latency for the storage operation satisfies an alert threshold a host is notified of compromised firmware.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Judah Gamliel HAHN, Shay Benisty, Ariel Navon
  • Publication number: 20220229566
    Abstract: The present disclosure generally relates to data storage devices, such as solid state drives, and effective power management of the data storage device. The data storage device includes a controller, where the controller is configured to predict when a host device will send a command to enter a low power state, prepare the data storage device to enter the low power state, and receive a command to enter the low power state after the predicting and preparing. If the data storage device is idled for greater than a threshold value, then the data storage device prepares to transition to a low power state but will wait to enter the lower power state until receiving a request from a host device.
    Type: Application
    Filed: February 25, 2021
    Publication date: July 21, 2022
    Inventors: Shay BENISTY, Judah Gamliel HAHN, Ariel NAVON
  • Publication number: 20220221997
    Abstract: Systems and methods for allocating storage based on aggregate performance of duplicate data are described. A number of duplicates of a host data unit in a storage medium may be determined, such as by a storage device and/or host device. Operation parameters for the duplicate host data may be aggregated into aggregate operation parameters. The aggregate operation parameters may be used to allocate storage in the storage medium, such as by determining target duplicate numbers and performance thresholds for deduplication and tiering decisions. Duplicate host data units may be stored, moved, or deleted based on the aggregate operation parameters.
    Type: Application
    Filed: February 23, 2021
    Publication date: July 14, 2022
    Inventors: Ariel Navon, Shay Benisty
  • Publication number: 20220221999
    Abstract: Systems and methods for deduplication of storage device encoded data are described. The storage device may initiate a deduplication process and determine a encoded target data block and at least one encoded comparison data block. The storage device may compare the encoded target data block to the encoded comparison data blocks to determine similarity values. Based on the similarity values, the storage device may determine duplicate data units and eliminate extra duplicate data units.
    Type: Application
    Filed: February 23, 2021
    Publication date: July 14, 2022
    Inventors: Ariel Navon, Shay Benisty
  • Patent number: 11386203
    Abstract: An apparatus, system, and method for detecting compromised firmware in a non-volatile storage device. A control bus of a non-volatile storage device is monitored. The non-volatile storage device includes a processor and electronic components coupled to the control bus. Signal traffic on the control bus is analyzed for events and/or triggers related to storage operations initiated on the control bus by the processor. Storage operations include one or more commands directed to at least one of the electronic components. If the latency for the storage operation satisfies an alert threshold a host is notified of compromised firmware.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: July 12, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Judah Gamliel Hahn, Shay Benisty, Ariel Navon
  • Publication number: 20220214835
    Abstract: An adaptive-feedback-based read-look-ahead management system and method are provided. In one embodiment, a method for stream management is presented that is performed in a storage system. The method comprises performing a read look ahead operation for each of a plurality of streams; determining a success rate of the read look ahead operation of each of the plurality of streams; and allocating more of the memory for a stream that has a success rate above a threshold than for a stream that has a success rate below the threshold. Other embodiments are provided.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon, Alexander Bazarsky
  • Patent number: 11379031
    Abstract: An apparatus includes memory arrays and a power-performance-endurance manager module. The power-performance-endurance manager module stores a power-endurance state descriptor data structure, which includes endurance levels associated with power-endurance modes. The manager module dynamically configures the apparatus to operate the memory arrays according to one of the power-endurance modes based on a desired endurance level.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 5, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ariel Navon, Eran Sharon, Shay Benisty
  • Patent number: 11366749
    Abstract: A storage system has a volatile memory, a non-volatile memory, and a controller. The controller of the storage system can implement various mechanisms for improving random read performance. These mechanisms include improved read prediction cache management, using a pattern length for read prediction, and a time-based enhancement for read prediction. Each of these mechanisms can be used alone on in combination with some or all of the other mechanisms.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: June 21, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon, Eran Sharon
  • Patent number: 11354454
    Abstract: An apparatus and method of providing direct access to a non-volatile memory of a non-volatile memory device and detecting potential security violations are provided. A method for providing access to a non-volatile memory of a non-volatile memory device may include tracking a parameter related to a plurality of direct access transactions of the non-volatile memory. A threshold behavior pattern of the host activity may be determined based upon the tracked parameters. The direct access transactions may be reviewed to determine whether the threshold behavior pattern is exceeded.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: June 7, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alon Marcu, Ariel Navon, Shay Benisty
  • Publication number: 20220171716
    Abstract: A storage system and method for providing a dual-priority credit system are disclosed. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive, from a host, a plurality of credits for sending messages to the host; allocate a first portion of the plurality of credits for non-urgent messages; and allocate a second portion of the plurality of credits for urgent messages. Other embodiments are provided.
    Type: Application
    Filed: February 18, 2021
    Publication date: June 2, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon, Judah Gamliel Hahn, Alon Marcu
  • Patent number: 11340810
    Abstract: Methods and apparatus for managing and optimizing data storage devices that include non-volatile memory (NVM) are described. One such method involves deriving a hint for one or more logical block addresses (LBAs) of a storage device based on information received from a host device and/or physical characteristics of the storage device, such as LBAs that are invalidated together; grouping the LBAs into one or more clusters of LBAs based on the derived hint and a statistical analysis of the physical characteristics of the storage devices; allocating available physical block addresses (PBAs) in the storage device to one of the LBAs based on the one or more clusters of LBAs to achieve optimization of a data storage device.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 24, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ariel Navon, Alexander Bazarsky, Judah Gamliel Hahn, Karin Inbar, Rami Rom, Idan Alrod, Eran Sharon
  • Patent number: 11334280
    Abstract: Systems and methods for compacting and anonymizing telemetry data in a storage system. A controller of a storage device may generate telemetry data based on collected features indicative of the performance of the storage device. The controller may store the telemetry data in the telemetry memory of the storage device. The controller may then transform the telemetry data into transformed telemetry data based on a dimension reduction algorithm, and transmit the transformed telemetry data to the host device.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: May 17, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ariel Navon, Alexander Bazarsky, Judah Gamliel Hahn
  • Publication number: 20220147440
    Abstract: A storage system has a volatile memory, a non-volatile memory, and a controller. The controller of the storage system can implement various mechanisms for improving random read performance. These mechanisms include improved read prediction cache management, using a pattern length for read prediction, and a time-based enhancement for read prediction. Each of these mechanisms can be used alone on in combination with some or all of the other mechanisms.
    Type: Application
    Filed: February 23, 2021
    Publication date: May 12, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon, Eran Sharon
  • Publication number: 20220147282
    Abstract: A storage system and method for implementing an encoder, decoder, and/or buffer using a field programmable gate array are provided. In one embodiment, a storage system is provided with a field programmable gate array and a memory that stores sets of instruction code for the field programmable gate array. The sets of instruction code can be for different error decoder implementations, for providing an additional encoder and/or decoder, or for implementing a host memory buffer or a controller memory buffer.
    Type: Application
    Filed: January 24, 2022
    Publication date: May 12, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ariel Navon, Ran Zamir, Shay Benisty
  • Publication number: 20220138541
    Abstract: Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may be a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, an NTM controller sets the size of the NTM matrix based on a storage access granularity of the NVM array. For instance, if the NVM reads and writes data in flash memory unit (FMUs), the NTM controller sets the size of the NTM matrix to correspond to the size of an integer number of FMUs. In some examples, the NVM array includes on-chip NTM circuitry configured to perform at least some NTM read head and write head operations. Threshold-based processing is described that can reduce an amount of NTM data read from the NVM array. In other examples, volatile memory is employed rather than an NVM array.
    Type: Application
    Filed: February 24, 2021
    Publication date: May 5, 2022
    Inventors: Alexander Bazarsky, Ariel Navon, Ofir Pele
  • Publication number: 20220107893
    Abstract: The present disclosure generally relates to improving write cache utilization by recommending a time to initiate a data flush operation or predicting when a new write command will arrive. The recommending can be based upon considerations such as a hard time limit for data caching, rewarding for filling the cache, and penalizing for holding data for too long. The predicting can be based on tracking write command arrivals and then, based upon the tracking, predicting an estimated arrival time for the next write command. Based upon the recommendation or predicting, the write cache can be flushed or the data can remain in the write cache to thus more efficiently utilize the write cache without violating a hard stop time limit.
    Type: Application
    Filed: March 24, 2021
    Publication date: April 7, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay BENISTY, Ariel NAVON
  • Patent number: 11294595
    Abstract: An adaptive-feedback-based read-look-ahead management system and method are provided. In one embodiment, a method for stream management is presented that is performed in a storage system. The method comprises performing a read look ahead operation for each of a plurality of streams; determining a success rate of the read look ahead operation of each of the plurality of streams; and allocating more of the memory for a stream that has a success rate above a threshold than for a stream that has a success rate below the threshold. Other embodiments are provided.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 5, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon, Alexander Bazarsky
  • Patent number: 11281981
    Abstract: A storage system and sorting-based method for random read command prediction in a multi-queue system are provided. In one embodiment, a method for command prediction is performed in a storage system comprising a memory and being in communication with a host. The method comprises receiving a read command sequence from the host, wherein read commands in the read command sequence originate from a plurality of command queues in the host such that read commands in the read command sequence received from the host are out of order; sorting read commands in the read command sequence received from the host based on logical block addresses; and predicting a next read command from the sorted read commands. Other embodiments are provided.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: March 22, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eran Sharon, Ariel Navon, Shay Benisty
  • Patent number: 11269764
    Abstract: A storage system and method for adaptive scheduling of background operations are provided. In one embodiment, after a storage system completes a host operation in the memory, the storage system remains in a high power mode for a period of time, after which the storage system enters a low-power mode. The storage system estimates whether there will be enough time to perform a background operation in the memory during the period of time without the background operation being interrupted by another host operation. In response to estimating that there will be enough time to perform the background operation in the memory without the background operation being interrupted by another host operation, the storage system performs the background operation in the memory.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 8, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Judah Gamliel Hahn, Alexander Bazarsky, Ariel Navon, David Gur
  • Patent number: 11269645
    Abstract: A storage system and method for implementing an encoder, decoder, and/or buffer using a field programmable gate array are provided. In one embodiment, a storage system is provided with a field programmable gate array and a memory that stores sets of instruction code for the field programmable gate array. The sets of instruction code can be for different error decoder implementations, for providing an additional encoder and/or decoder, or for implementing a host memory buffer or a controller memory buffer.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: March 8, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ariel Navon, Ran Zamir, Shay Benisty