Abstract: The present disclosure generally relates partial speed changes to improve in-order data transfer. Rather than determining an ECC decoder on a first available decoder basis, the ECC decoder may be based on the ECC decoder level. A memory device will have at least one FMU that has a syndrome weight (SW). The disclosure proposes assigning FMU's based on the SW rate. At the time the command is read, the data storage device determines which level of decoder will be assigned to the FMU. The determination will then be checked according to different system environment parameters to maintain performance or reduce power consumption. The arrangement allows a more flexible system design that can adapt according to the current system status.

Abstract: A data storage device and method for device-initiated hibernation are provided. In one embodiment, the data storage device comprises a non-volatile memory and a controller. The controller is configured to: receive, from a host during a set-up phase of a hibernation process, a plurality of write commands with a current state of a volatile memory in the host; store the plurality of write commands in a queue, wherein the plurality of write commands are not executed during the set-up phase of the hibernation process; receive a trigger from the host to perform an execution phase of the hibernation process; and in response to receiving the trigger, execute the plurality of write commands to store the current state of the host's volatile memory in the non-volatile memory of the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A data storage device comprises a first memory, a second memory, and a controller. The first memory has a faster access time than the second memory. The controller is configured to store host-initialization code in the first memory, store a copy of the host-initialization code in the second memory, determine that the copy of the host-initialization code should be designated as the main version of the host-initialization code, and relocate the copy of the host-initialization code to the first memory, which makes the copy of the host-initialization code the main version of the host-initialization code that is accessed to boot-up the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: The present disclosure generally relates to estimating when data to be written will be read or re-written prior to actually writing the data to the memory device. The estimating can be used to smartly route the data to the appropriate memory location at the writing stage or to evict the data from a hot memory location to a colder memory location. To perform the estimating, typical traces or data may be used as may the metadata of the data. Separating data according to the data “temperature” (i.e. the expected access time and frequency), and usage to optimize the SLC partition usage has meaningful impact on several storage metrics such as performance and endurance.

Abstract: The present disclosure generally relates to detecting command identification (CID) collisions in host commands. Host commands stored in submission queues are supposed to have unique CIDs. The host device selects the CID and attaches the CID to the command. Once the command is executed, the host device may reuse the CID. Sometimes, the host device reuses a CID before a command already using the CID is executed, which is a collision. Rather than search all CIDs to find a collision, redundancy bits can be created for each command, and the redundancy can be the same for multiple pending commands. The redundancy bits can be checked first to see if there is a match, followed by comparing CIDs for only those commands that have matching redundancy bits. In so doing, CID collisions are detected earlier and easier.

Abstract: A data storage device and method for file-based interrupt coalescing are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to execute a plurality of read commands read from a submission queue in a host; write a plurality of completion messages to a completion queue in the host; and coalesce interrupts to inform the host that plurality of completion messages were written to the completion queue; wherein the submission queue and the completion queue are dedicated to read commands from a host application and are separate from a submission queue and a completion queue for read and write commands from an operating system of the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: The present disclosure generally relates to detecting command identification (CID) collisions in host commands. Host commands stored in submission queues are supposed to have unique CIDs. The host device selects the CID and attaches the CID to the command. Once the command is executed, the host device may reuse the CID. Sometimes, the host device reuses a CID before a command already using the CID is executed, which is a collision. Rather than search all CIDs to find a collision, redundancy bits can be created for each command, and the redundancy can be the same for multiple pending commands. The redundancy bits can be checked first to see if there is a match, followed by comparing CIDs for only those commands that have matching redundancy bits. In so doing, CID collisions are detected earlier and easier.

Abstract: A data storage device includes a memory device, an always on (AON) application specific integrated circuit (ASIC), and a controller coupled to the memory device and the AON ASIC. When the data storage device enters a low power state, the controller generates and stores security data associated with context data in a power management integrated circuit (PMIC). The context data is stored in both the memory device and a host memory buffer (HMB). A location of the context data in the HMB is stored in the PMIC with the security data. When the data storage device exits the low power state, the address stored in the PMIC is utilized to retrieve the context data from the HMB. The retrieved context data is verified against the security data by the controller.

Abstract: Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.

Abstract: A storage system and method for providing a dual-priority credit system are disclosed. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive, from a host, a plurality of credits for sending messages to the host; allocate a first portion of the plurality of credits for non-urgent messages; and allocate a second portion of the plurality of credits for urgent messages. Other embodiments are provided.

Abstract: The present disclosure generally relates to reducing boot latency of memory devices in a dual boot system. The boot code is loaded to the data storage device controller in a flexible manner by being able to receive chunks of the boot code from two separate locations, the host memory buffer (HMB) and the memory device, which may be a NAND device. Part of the boot code may be received from the HMB and another part of the boot code may be received from the memory device. If either the HMB or the memory device can deliver the chunks faster than the other, then the controller can receive the chunks from the faster location and periodically confirm the speed of delivery to ensure the boot code latency is optimized.

Abstract: A data storage device includes a memory and a controller coupled to the memory device. The controller is configured to be coupled to a host device. The controller is further configured to receive a plurality of commands, generate logical block address (LBA) to physical block address (PBA) (L2P) mappings for each of the plurality of commands, and store data of the plurality of commands to a respective PBA according to the generated L2P mappings. Each of the L2P mappings are generated based on a result of a deep learning (DL) training model using a neural network (NN) structure. The controller includes a NN command interpretation unit and a L2P mapping generator coupled to the NN command interpretation unit. The controller is configured to fetch training data and NN parameters from the memory device.

Abstract: The present disclosure generally relates to utilizing improved DL training models stored in non-volatile memory to optimize data transfer and storage. The proposed system would identify workloads of DNN training and occasionally check the difference rate between successive data transfers (representing successive training iterations of the model). Comparing the difference rate to given thresholds could indicate “recommendation-system” typical use case. In such a case the NAND operating system would apply systematic compression of the data by saving only the changed parameters between successive iteration cycles (“batches”). The host may indicate the checkpoint storage configuration of the training model (every iteration, every several iterations etc. . . . ) and other elements. The system may be efficiently utilized combining the NAND based DNN training interface, adding the checkpoint configuration information to the dedicated interface.

Abstract: A method and system for maintaining coherency between DMA and NVMe data paths are disclosed. As DMA requests are received in the PMR region, a device controller will translate these into NVMe commands with a dedicated queue that is hidden from a host that has higher priority than the corresponding host (NVMe) commands. The payload returned from an internally executed NVMe command is stored in a buffer used to complete the DMA request. As memory reads are submitted, the controller will mark corresponding LBA ranges for overlap, ensuring coherency between these reads and writes from other queues. Since the internal PMR queue has a higher priority than host-facing queues (e.g., NVMe), and the PMR is read-only, read coherency against host writes to the same region may be achieved.

Abstract: A data storage device and method for providing an adaptive data path are disclosed. In one embodiment, a data storage device is in communication with a host comprising a first processor (e.g., a graphics processing unit (GPU)), a second processor (e.g., a central processing unit (CPU)), and a queue. The data storage device chooses a data path to use to communicate with the queue based on whether the queue is associated with the first processor or with the second processor. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: The present disclosure generally relates to improving data transfer in a data storage device. In double data rate (DDR) systems that include a data bus inversion (DBI) functionality, bit flip events can be more prevalent. To mitigate the effect of enhanced erroneous bit flip rate related to DBI bit flip events, the DBI bit can stay static for a predetermined number of consecutive clock cycles, the error correction module can be informed of reduced reliability due to active DBI bit events, the DBI bit can be set to 0, or combinations thereof. Setting the DBI bit to 0 effectively cancels DBI functionality. Informing the error correction module permits a more robust error correction to occur. Forcing the DBI bit to remain static reduces the probability of an unrecognized bit flip event of a full byte. In so doing, data transfer reliability is improved when using DBI functionality.

Abstract: Apparatuses and methods of directly accessing a memory space of a storage device by a host are provided. In one embodiment, a method of driverless access of a non-volatile memory of a non-volatile memory device by a host includes initializing a PCIe memory space mapping a portion of the non-volatile memory of the non-volatile memory device to a host memory space. The non-volatile memory is mapped through a PCIe link between the host and the non-volatile memory device. Load/store commands are sent to the PCIe memory space for driverless access. The method further includes negotiating an alignment size of the minimum transaction packet size to complete the load/store commands.

Abstract: A method and apparatus for cache management and eviction polices using unsupervised reinforcement learning schemes is disclosed.

Abstract: A method and apparatus for video processing on a data storage device. A chip bound architecture includes a CMOS coupled to one or more NAND die, the CMOS including one or more processors, memories, and error correction code (ECC) engines capable of processing video data. According to certain embodiments, macroblocks are correlated between two I-frames, including motion vectors to define different locations of correlated macroblocks. A P-frame may be determined from a previous I-frame and its correlated macroblocks and motion vectors, while a B-frame may be determined from two or more adjacent I-frames with concomitant macroblocks and motion vectors, as well as P-frames associated with an adjacent I-frame.

Abstract: An apparatus, system, and method for detecting compromised firmware in a non-volatile storage device. A control bus of a non-volatile storage device is monitored. The non-volatile storage device includes a processor and electronic components coupled to the control bus. Signal traffic on the control bus is analyzed for events and/or triggers related to storage operations initiated on the control bus by the processor. Storage operations include one or more commands directed to at least one of the electronic components. If the latency for the storage operation satisfies an alert threshold a host is notified of compromised firmware.