Patents by Inventor Arindam Chatterjee
Arindam Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100107218Abstract: Systems and methods that establish a secured compartment that manages sensitive user transactions/information on a user's machine. The secured compartment qualifies user interaction with the machine, and separates such qualified interaction from other user activity on the machine. A user is switched to such secured compartment upon occurrence of a predetermined event, such as in form of: an explicit request (e.g., a secure attention sequence); an implicit request (e.g., inference of user activities); and presence of a peripheral device that is bound to the secured compartment (e.g., a USB)—wherein such actions typically cannot be generated by an application running outside the secured compartment.Type: ApplicationFiled: October 24, 2008Publication date: April 29, 2010Applicant: MICROSOFT CORPORATIONInventors: Thekkthalackal Varugis Kurien, Cormac E. Herley, Alice Jane Bernheim Brush, Daniel C. Robbins, Arindam Chatterjee, Scott Field
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Patent number: 7511065Abstract: The present invention provides a compound of the formula: (Formula I); or a pharmaceutically acceptable salt thereof, pharmaceutical compositions comprising an effective amount of a compound of Formula I in combination with a suitable carrier, diluent, or excipient, and methods for treating physiological disorders, particularly congestive heart disease, comprising administering to a patient in thereof an effective amount of a compound of Formula I.Type: GrantFiled: November 12, 2003Date of Patent: March 31, 2009Assignee: Eli Lilly and CompanyInventors: Theodore Goodson, Jr., Mary Margaret Mader, John Eldon Toth, Arindam Chatterjee, Jason Scott Sawyer
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Publication number: 20090007264Abstract: A security system is provided for use with computer systems. In various embodiments, the security system can analyze the state of security of one or more computer systems to determine whether the computer systems comply with expressed security policies and to remediate the computer systems so that they conform with the expressed security policies. In various embodiments, the security system can receive compliance documents, determine whether one or more computer systems comply with portions of security policies specified in the compliance documents, and take actions specified in the compliance documents to cause the computer systems to comply with the specified security policies. The security system may provide a common, unified programming interface that applications or tools can employ to verify or enforce security policies.Type: ApplicationFiled: June 26, 2007Publication date: January 1, 2009Applicant: Microsoft CorporationInventors: Arindam Chatterjee, Anders Samuelsson, Nils Dussart, Charles G. Jeffries, Amit R. Kulkarni
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Publication number: 20080244690Abstract: Systems and methods that automatically generate remediation processes such as acts performed as part of a benchmark model, to improve and update compliance of a machine with security policies compliance. A remediation component can automatically determine processes that are required to change and increase compliance of a machine with a security policy, and hence improve security level thereof.Type: ApplicationFiled: April 2, 2007Publication date: October 2, 2008Applicant: MICROSOFT CORPORATIONInventors: Amit Raghunath Kulkarni, Arindam Chatterjee, Tristan Brown
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Publication number: 20080113977Abstract: The present invention provides a compound of the formula: (Formula I); or a pharmaceutically acceptable salt thereof, pharmaceutical compositions comprising an effective amount of a compound of Formula I in combination with a suitable carrier, diluent, or excipient, and methods for treating physiological disorders, particularly congestive heart disease, comprising administering to a patient in thereof an effective amount of a compound of Formula I.Type: ApplicationFiled: November 12, 2003Publication date: May 15, 2008Inventors: Arindam Chatterjee, Theodore Goodson Jr, Mary Margaret Mader, John Eldon Toth
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Publication number: 20080115218Abstract: A security health reporting system provides an application program interface (API) for use by independent software vendors (ISVs) to extend the security health reporting capabilities of the security health reporting system. An ISV security solution can register with the security health reporting system, create a schema that describes a new security class, and use the API to publish an instance of the schema for the new security class with the security health reporting system. When an instance of a schema for a new security class is published, the security health reporting system creates the new security class, and recognizes the definition for the security class within the security health reporting system. Registered ISV security solutions can then use the published schema to report their health statuses for the new security class.Type: ApplicationFiled: November 10, 2006Publication date: May 15, 2008Applicant: Microsoft CorporationInventors: Charles G. Jeffries, Doug Coburn, Barry Gerhardt, Randall K. Winjum, Arindam Chatterjee
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Publication number: 20070198525Abstract: A managed network with a quarantine enforcement policy based on the status of installed updates for software on each client seeking access to the managed network. To determine whether a client requesting access has up-to-date software, an access server may communicate directly with an update server to determine the update status of the client requesting access. Information from the update server allows the update server to determine which update the client requesting access is missing. The access server may also receive an indication of the severity of the updates missing from the client requesting access. The access server may use the severity information to apply a quarantine enforcement policy, thereby avoiding the need for either the client or access server to be programmed to identify specific software updates that must be installed for a client to comply with a quarantine enforcement policy.Type: ApplicationFiled: February 13, 2006Publication date: August 23, 2007Applicant: Microsoft CorporationInventors: Arindam Chatterjee, Bashar Kachachi, Bruce Leban, Calvin Choe, Charles Jeffries, Jeffrey Shipman, Lakshmanan Venkitaraman, Marc Shepard, Sachin Sheth, Shankar Seal, Yang Gao, Patrick Stratton, Michael Lee
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Patent number: 7114138Abstract: The present invention introduces novel methods of performing integrated circuit layout extraction. In the system of the present invention, complex resistance extraction problem is first broken down into a set of smaller extraction sub problems. Some of the smaller extraction sub problems may be handled by simple parametric models. For example, extracting the resistance from a straight section of interconnect wire may be performed by multiplying a known resistance per unit length by the length of the straight section of interconnect wire. For more complex resistance extraction sub problems, machine learning is used to build models.Type: GrantFiled: December 31, 2002Date of Patent: September 26, 2006Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Arindam Chatterjee
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Patent number: 7103524Abstract: A system for using machine learning based upon Bayesian inference using a hybrid Monte Carlo method to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Then, for each of the smaller simpler extraction problems, complex mathematical models are created using machine learning techniques.Type: GrantFiled: January 31, 2002Date of Patent: September 5, 2006Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Arindam Chatterjee
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Method and arrangement for extracting capacitance in integrated circuits having non manhattan wiring
Patent number: 7086021Abstract: A method of extracting capacitance for a first wire segment is disclosed. The method approximates a non orthogonal first section of interconnect wiring containing the first wire segment by using an orthogonal second section of interconnect wiring. The method determines an estimated capacitance of the non orthogonal first section of interconnect wiring by using the orthogonal second section of interconnect wiring. The method adds a correction factor to the estimated capacitance to generate a modeled capacitance value for the non orthogonal first section of interconnect wiring.Type: GrantFiled: November 26, 2004Date of Patent: August 1, 2006Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Arindam Chatterjee -
Patent number: 7051293Abstract: A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, models are created using machine learning techniques for all of the smaller simpler extraction problems. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver. The training sets are then used to train the models.Type: GrantFiled: January 31, 2002Date of Patent: May 23, 2006Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Arindam Chatterjee
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Publication number: 20060005227Abstract: Languages for expressing security policies are provided. The languages comprise rules that specify conditions and actions. The rules may be enforced by a security engine when a security enforcement event occurs. The languages support data separation, dynamic evaluation, and ordered rule scope. By separating data from logic, security engines may only need to be updated with a portion of rules that change. With dynamic evaluation, expressions of rules may be evaluated dynamically, such as by querying a database, when a security engine enforces a rule. With ordered rule scope, when a security enforcement event implicates a number of rules simultaneously, the rules may be enforced in a deterministic and logically organized manner.Type: ApplicationFiled: July 1, 2004Publication date: January 5, 2006Applicant: Microsoft CorporationInventors: Anders Samuelsson, Thomas Fakes, Arindam Chatterjee, Art Shelest, Mark Vayman, Rajesh Dadhia, Saveen Reddy, Shirish Koti, Steven Townsend
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Patent number: 6961914Abstract: The present invention introduces novel methods generating training data for machine learning models that will be used for extraction. Specifically, experimental design is employed to select a set of training points that provide the best information. In one embodiment, the training point set is created by creating a critical input spanning set, adding training points from critical regions in the input space, and adding training points from frequently encountered profile cases. The training point set then used to train a machine learning built model such as a neural network or support vector machine that will extract electrical characteristics.Type: GrantFiled: December 31, 2002Date of Patent: November 1, 2005Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Arindam Chatterjee
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Patent number: 6941531Abstract: The present invention introduces novel methods of performing integrated circuit layout extraction. In the system of the present invention, a complex extraction problem is first broken down into a set of smaller extraction sub problems. Some of the smaller extraction sub problems may be handled by simple parametric models. For example, extracting the resistance from a straight section of interconnect wire may be performed by multiplying a known resistance per unit length by the length of the straight section of interconnect wire. For more complex extraction sub problems, machine learning is used to build models. In one embodiment, Support Vector Machines are constructed to extract the desired electrical characteristics.Type: GrantFiled: December 31, 2002Date of Patent: September 6, 2005Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Arindam Chatterjee
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Patent number: 6925618Abstract: The present invention introduces novel methods of performing integrated circuit layout extraction. In the system of the present invention, a complex extraction problem is first broken down into a set of smaller extraction sub problems. Some of the smaller extraction sub problems may be handled by simple parametric models. However, for the frequent complex extraction sub problems, machine learning is used to build models. Specifically, Support Vector Machines are constructed to extract the desired electrical characteristics. To build the Support Vector Machines, Experimental design is employed to select a set of training points that provide the best information. In one embodiment, the training point set is created by creating a critical input spanning set, adding training points from critical regions in the input space, and adding training points from frequently encountered profile cases.Type: GrantFiled: December 31, 2002Date of Patent: August 2, 2005Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Arindam Chatterjee
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Patent number: 6907591Abstract: A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, models are created using machine learning techniques for all of the smaller simpler extraction problems. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver.Type: GrantFiled: January 31, 2002Date of Patent: June 14, 2005Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Arindam Chatterjee
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Patent number: 6892366Abstract: A system for using machine learning based upon Bayesian inference using a hybrid monte carlo method to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, complex mathematical models are created using machine learning techniques for all of the smaller simpler extraction problems.Type: GrantFiled: January 31, 2002Date of Patent: May 10, 2005Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Arindam Chatterjee
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Method and arrangement for extracting capacitance in integrated circuits having non manhattan wiring
Publication number: 20050091619Abstract: A method of extracting capacitance for a first wire segment is disclosed. The method approximates a non orthogonal first section of interconnect wiring containing the first wire segment by using an orthogonal second section of interconnect wiring. The method determines an estimated capacitance of the non orthogonal first section of interconnect wiring by using the orthogonal second section of interconnect wiring. The method adds a correction factor to the estimated capacitance to generate a modeled capacitance value for the non orthogonal first section of interconnect wiring.Type: ApplicationFiled: November 26, 2004Publication date: April 28, 2005Inventors: Steven Teig, Arindam Chatterjee -
Patent number: 6883148Abstract: A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, models are created using machine learning techniques for all of the smaller simpler extraction problems. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver.Type: GrantFiled: January 31, 2002Date of Patent: April 19, 2005Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Arindam Chatterjee
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Patent number: 6880138Abstract: The present invention introduces novel methods of generating input vectors for machine learning system that will perform extraction. Experimental design is employed to select a set of training points that provide the best information. In one embodiment, a set of input vectors and output vectors are analyzed to determine a set of critical input parameters. Then, a spanning point generation program is used to generate a set of spanning points that cover the identified critical input space. The training point set then used to train a machine learning model.Type: GrantFiled: December 31, 2002Date of Patent: April 12, 2005Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Arindam Chatterjee