Patents by Inventor Arindam Chatterjee

Arindam Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6857112
    Abstract: A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, models are created using machine learning techniques for all of the smaller simpler extraction problems. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver. The training sets are then used to train the models.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: February 15, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Arindam Chatterjee
  • Patent number: 6854101
    Abstract: The present invention introduces a method of quickly extracting the capacitance for interconnect wires in an integrated circuit routed with a non Manhattan architecture. To extract the capacitance a section containing non Manhattan wiring, the present invention proposes an approximation system that approximates the section of non Manhattan wiring with a Manhattan wiring section that has a capacitance per unit length that is generally proportional to the length of the approximated section. The capacitance effect from the approximated Manhattan wiring section may then be adjusted with a correction factor.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: February 8, 2005
    Assignee: Cadence Design Systems Inc.
    Inventors: Steven Teig, Arindam Chatterjee
  • Publication number: 20040224958
    Abstract: This invention provides pyridopyrimidines and 4-aminopyrimidines that are useful for treating cell proliferatives disorders, such as cancer and restenosis. We have now discovered a group of 7,8-dihydro-2 (amino and thio)pyrido[2,3-d]pyrimidines and 2,4-diaminopyrimidines that are potent inhibitors of cyclin-dependent kinases (cdks) and growth factor-mediated kinases. The compounds are readily synthesized and can be administered by a variety of routes, including orally, and have sufficient bioavailability. This invention provides compounds of Formula (I) and Formula (II) where W is NH, S, SO, or SO2, R1 includes phenyl and substituted phenyl, R2 includes alkyl and cycloalkyl, R3 includes alkyl and hydrogen, R8 and R9 include hydrogen and alkyl, and Z is carboxy. This invention also provide pharmaceutical formulations comprising a compound of Formula (I or II) together with a pharmaceutically acceptable carrier, diluent, or excipient therefor.
    Type: Application
    Filed: November 12, 2002
    Publication date: November 11, 2004
    Inventors: Richard John Booth, Arindam Chatterjee, Thomas Charles Malone
  • Patent number: 6735748
    Abstract: A machine-learning model may be created to perform integrated circuit layout extraction. Using such a machine-learning system has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver. Next, the system performs machine learning using Bayesian inference in order to train the neural network models. The Bayesian inference may be implemented with normal Monte Carlo techniques, Hybrid Monte Carlo techniques, or other Bayesian learning techniques. After the creation of a set of models for each of the smaller simpler extraction problems, the machine-learning based models may be used for extraction.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: May 11, 2004
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Arindam Chatterjee
  • Publication number: 20040049751
    Abstract: The present invention introduces a method of quickly extracting the capacitance for interconnect wires in an integrated circuit routed with a non Manhattan architecture. To extract the capacitance a section containing non Manhattan wiring, the present invention proposes an approximation system that approximates the section of non Manhattan wiring with a Manhattan wiring section that has a capacitance per unit length that is generally proportional to the length of the approximated section. The capacitance effect from the approximated Manhattan wiring section may then be adjusted with a correction factor.
    Type: Application
    Filed: May 9, 2003
    Publication date: March 11, 2004
    Inventors: Steven Teig, Arindam Chatterjee
  • Patent number: 6687887
    Abstract: A system for using machine learning based upon Bayesian inference using a hybrid monte carlo method to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, complex mathematical models are created using machine learning techniques for all of the smaller simpler extraction problems.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: February 3, 2004
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Arindam Chatterjee
  • Patent number: 6581198
    Abstract: The present invention introduces a method of quickly extracting the capacitance for interconnect wires in an integrated circuit routed with a non Manhattan architecture. To extract the capacitance a section containing non Manhattan wiring, the present invention proposes an approximation system that approximates the section of non Manhattan wiring with a Manhattan wiring section that has a capacitance per unit length that is generally proportional to the length of the approximated section. The capacitance affect from the approximated Manhattan wiring section is then adjusted with a correction factor.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: June 17, 2003
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Arindam Chatterjee