Abstract: A printed circuit board (PCB) stack-up has a signal via configured to transmit a signal through at least two different layers of the PCB stack-up, a reference structure that is at least a portion of a return path for the signal; and an unplated via disposed in an area surrounding the signal via. The unplated via is disposed in the area surrounding the signal via to improve the characteristic impedance of the signal via.

Abstract: A printed circuit board (PCB) stack-up has a signal via configured to transmit a signal through at least two different layers of the PCB stack-up, a reference structure that is at least a portion of a return path for the signal; and an unplated via disposed in an area surrounding the signal via. The unplated via is disposed in the area surrounding the signal via to improve the characteristic impedance of the signal via.

Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate further includes at least one signal layer having a plurality of electrical signal traces formed thereon. The package includes a discrete non-active electrical component mounted on the package so that the integrated circuit die is electrically connected with an electrical signal trace of the package through the discrete non-active electrical component. And in one particular implementation, the discrete non-active electrical component comprises a capacitive element arranged in series between the electrical signal traces and the die so that the capacitor operates as a package mounted AC coupling capacitor.

Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.

Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.

Abstract: A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern, where the third portion of the pattern is disposed in an interior portion of the pattern relative to both the first portion of the pattern and the second portion of the pattern.

Abstract: A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern, where the third portion of the pattern is disposed in an interior portion of the pattern relative to both the first portion of the pattern and the second portion of the pattern.

Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.

Abstract: A substrate is provided, which has a pattern of voltage supply vias extending through at least a portion of the substrate. Each of a plurality of the voltage supply vias is surrounded by four of the voltage supply vias of a same polarity in four orthogonal directions and by four voltage supply vias of an opposite polarity in four diagonal directions.

Abstract: A method of designing a packaged circuit, including a substrate and a circuit. The circuit is designed with a plurality of standardized functional blocks. Each of the functional blocks has a known function and a known contact pattern. The circuit is designed by selecting desired functional blocks according to functions desired for the circuit. The substrate is designed with a plurality of standardized functional blocks. Each of the functional blocks has a known contact pattern, a known signal trace routing layer pattern, a known ground plane layer pattern, and a known power plane layer pattern. A given one of the substrate functional blocks is associated with a given one of the circuit functional blocks. The substrate is designed by selecting substrate functional blocks associated with the desired ones of the circuit functional blocks.

Abstract: A tester head from a tester is used to mount a probe card. A DUT/load board has a socket which is configured to hold a substrate. Probe pins from the probe card make contact with bump pads on the substrate. Signal wires from the DUT/load board are fed to the tester, and the tester is connected to a DSO with a fast rise time signal head. During testing, a signal is launched using the DSO into a coaxial cable which is connected to the test head. The launched signal and the reflected signal are captured back by the DSO, and then fed into the tester. Using this data, post processing software is used to obtain the interconnect impedance versus time for the device (i.e., package) under test. The method and apparatus can be used in connection with both Flip Chip and Wire bonded products.

Abstract: A probe structure for testing impedance of a package substrate using time domain reflectometry. A connector electrically connects the probe structure to a time domain reflectometry tester, where the connector has a signal conductor and a ground conductor. An electrically conductive cantilever signal pin is electrically connected to the signal conductor. The electrically conductive cantilever signal pin has a tip for making an electrical connection with an electrically conductive structure to be tested on the package substrate. The electrically conductive cantilever signal pin is electrically isolated by and sheathed within a ground shield that is electrically connected to at least one of the ground conductor and electrically conductive cantilever ground pins. The electrically conductive cantilever ground pins are electrically connected to the ground conductor.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate further includes at least one signal layer having a plurality of electrical signal traces formed thereon. The package includes a discrete non-active electrical component mounted on the package so that the integrated circuit die is electrically connected with an electrical signal trace of the package through the discrete non-active electrical component. And in one particular implementation, the discrete non-active electrical component comprises a capacitive element arranged in series between the electrical signal traces and the die so that the capacitor operates as a package mounted AC coupling capacitor.

Abstract: A method of designing a packaged circuit, including a substrate and a circuit. The circuit is designed with a plurality of standardized functional blocks. Each of the functional blocks has a known function and a known contact pattern. The circuit is designed by selecting desired functional blocks according to functions desired for the circuit. The substrate is designed with a plurality of standardized functional blocks. Each of the functional blocks has a known contact pattern, a known signal trace routing layer pattern, a known ground plane layer pattern, and a known power plane layer pattern. A given one of the substrate functional blocks is associated with a given one of the circuit functional blocks. The substrate is designed by selecting substrate functional blocks associated with the desired ones of the circuit functional blocks.

Abstract: A method of forming a photo-resist image on a substrate, such as a conductive film. The method provides that a photo-resist image is printed directly onto the conductive film, such as by using an ink jet printer. Specifically, a CAD image may be sent from a computer to the ink jet printer, and the ink jet printer may use the CAD image to print the photo-resist image. The method may provide that a copper film is applied to a dielectric substrate, and then the photo-resist image is printed directly onto the copper film. Then, at least a portion of the copper film is removed, such as by etching, and at least a portion of the photo-resist image which has been printed on the copper film is removed, such as by etching. By printing the photo-resist image directly onto the copper film, it is not necessary to perform steps such as: applying a mask, exposing to UV light, and developing.

Abstract: A tester head from a tester is used to mount a probe card. A DUT/load board has a socket which is configured to hold a substrate. Probe pins from the probe card make contact with bump pads on the substrate. Signal wires from the DUT/load board are fed to the tester, and the tester is connected to a DSO with a fast rise time signal head. During testing, a signal is launched using the DSO into a coaxial cable which is connected to the test head. The launched signal and the reflected signal are captured back by the DSO, and then fed into the tester. Using this data, post processing software is used to obtain the interconnect impedance versus time for the device (i.e., package) under test. The method and apparatus can be used in connection with both Flip Chip and Wire bonded products.

Abstract: A method for fabricating a semiconductor package having a 2-layer substrate, which includes an array of solder balls, is disclosed. The method includes patterning signal traces on a top layer of the substrate and identifying groups of signal traces to isolate. According to the present invention, a grounded isolation trace is then patterned adjacent to one of the groups of traces to isolate the signal traces, thereby providing noise shielding. In a preferred embodiment, the grounded isolation trace is provided with multiple vias, rather than only one. In a further aspect of the present invention a row of solder balls is connected together and to ground to create a bottom-layer isolating ground trace to further reduce noise. The bottom-layer isolating ground trace may be connected to the top-layer isolating ground trace using a via.

Abstract: A stiffener for reinforcing a package integrated circuit. The stiffener includes a rigid planar element having a first surface for bonding to a package substrate. The rigid planar element forms a major interior aperture for receiving and surrounding an integrated circuit on all sides of the integrated circuit. The rigid planar element also forms a minor interior aperture for receiving and surrounding a secondary circuit structure on at least three sides of the secondary circuit structure. In this manner, the stiffener provides structural support to the integrated circuit package, which reduces and preferably eliminates twisting and warping of the substrate package as it heats and is subjected to other stresses.

Abstract: A package substrate is contemplated herein for reducing cross-talk for noise-sensitive signals. The package substrate includes noise-sensitive conductors adapted to receive the noise-sensitive signals. In one embodiment, the cross-sectional width of the noise-sensitive conductors is increased to reduce certain parasitic effects such as resistance and/or inductance. The package substrate also includes guard conductors which are arranged co-planar with and substantially parallel to the noise-sensitive conductors. A plurality of vias spaced equidistant from one another extends from a ground conductor to the guard conductors, providing a substantially uniform voltage across the guard conductors. The overall effect will reduce the inductive and capacitive cross-talk from neighboring signals and increase the signal integrity of noise-sensitive signals.