Patents by Inventor Arito Ogawa
Arito Ogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140242790Abstract: A metal-containing film capable of adjusting a work function is formed. A first source containing a first metal element and a halogen element and a second source containing a second metal element different from the first metal element and an amino group are alternately supplied onto a substrate having a high-k dielectric film to form a composite metal nitride film on the high-k dielectric film.Type: ApplicationFiled: February 24, 2014Publication date: August 28, 2014Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Kazuhiro HARADA, Arito OGAWA, Hiroshi ASHIHARA
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Publication number: 20140179086Abstract: A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate.Type: ApplicationFiled: February 26, 2014Publication date: June 26, 2014Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Arito OGAWA, Tsuyoshi TAKEDA
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Patent number: 8741731Abstract: A high-k capacitor insulating film stable at a higher temperature is formed. There is provided a method of manufacturing a semiconductor device. The method comprises: forming a first amorphous insulating film comprising a first element on a substrate; adding a second element different from the first element to the first amorphous insulating film so as to form a second amorphous insulating film on the substrate; and annealing the second amorphous insulating film at a predetermined annealing temperature so as to form a third insulating film by changing a phase of the second amorphous insulating film. The concentration of the second element added to the first amorphous insulating film is controlled according to the annealing temperature.Type: GrantFiled: December 13, 2012Date of Patent: June 3, 2014Assignee: Hitachi Kokusai Electric Inc.Inventors: Yuji Takebayashi, Hirohisa Yamazaki, Sadayoshi Horii, Hideharu Itatani, Arito Ogawa
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Publication number: 20140084389Abstract: Provided are a semiconductor device manufacturing method by which a semiconductor device in which a threshold voltage is suppressed from changing can be manufactured, a substrate processing method and apparatus, a non-transitory computer-readable recording medium, and the semiconductor device. The semiconductor device manufacturing method includes forming an amorphous first oxide film including a first element on a substrate, and modifying the first oxide film to an amorphous second oxide film including the first element and a second element different from the first element by adding the second element to the first oxide film. The first element includes at least one element selected from a group consisting of aluminum, yttrium and lanthanum. A concentration of the second element in the second oxide film is controlled to be lower than that of the first element in the second oxide film.Type: ApplicationFiled: September 25, 2013Publication date: March 27, 2014Applicant: Hitachi Kokusai Electric Inc.Inventor: Arito Ogawa
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Publication number: 20130309876Abstract: A method of manufacturing a semiconductor device includes: housing a substrate into a processing chamber; and forming a metal nitride film on the substrate by supplying a source gas containing a metal element, a nitrogen-containing gas and a hydrogen-containing gas into the processing chamber; wherein in forming the metal nitride film, the source gas and the nitrogen-containing gas are intermittently supplied into the processing chamber, or the source gas and the nitrogen-containing gas are intermittently and alternately supplied into the processing chamber, or the source gas is intermittently supplied into the processing chamber in a state that supply of the nitrogen-containing gas into the processing chamber is continued, and the hydrogen-containing gas is supplied into the processing chamber during at least supply of the nitrogen-containing gas into the processing chamber.Type: ApplicationFiled: November 29, 2011Publication date: November 21, 2013Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventor: Arito Ogawa
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Patent number: 8420552Abstract: A high-k capacitor insulating film stable at a higher temperature is formed. There is provided a method of manufacturing a semiconductor device. The method comprises: forming a first amorphous insulating film comprising a first element on a substrate; adding a second element different from the first element to the first amorphous insulating film so as to form a second amorphous insulating film on the substrate; and annealing the second amorphous insulating film at a predetermined annealing temperature so as to form a third insulating film by changing a phase of the second amorphous insulating film. The concentration of the second element added to the first amorphous insulating film is controlled according to the annealing temperature.Type: GrantFiled: July 30, 2010Date of Patent: April 16, 2013Assignee: Hitachi Kokusai Electric Inc.Inventors: Yuji Takebayashi, Hirohisa Yamazaki, Sadayoshi Horii, Hideharu Itatani, Arito Ogawa
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Patent number: 8404603Abstract: A method of manufacturing a semiconductor device. In the method, an aluminum-containing insulation film is formed on an electrode film of a substrate by alternately repeating a process of supplying an aluminum precursor into a processing chamber in which the substrate is accommodated and exhausting the aluminum precursor from the processing chamber and a process of supplying an oxidizing or nitriding precursor into the processing chamber and exhausting the oxidizing or nitriding precursor from the processing chamber; and a high permittivity insulation film different from the aluminum-containing insulation film is formed on the aluminum-containing insulation film by alternately repeating a process of supplying a precursor into the processing chamber and exhausting the precursor from the processing chamber and a process of supplying an oxidizing precursor into the processing chamber and exhausting the oxidizing precursor from the processing chamber. In addition, heat treatment is performed on the substrate.Type: GrantFiled: June 28, 2010Date of Patent: March 26, 2013Assignee: Hitachi Kokusai Electric Inc.Inventors: Arito Ogawa, Sadayoshi Horii, Taketoshi Sato, Hideharu Itatani, Nobuyuki Mise, Osamu Tonomura
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Publication number: 20130065391Abstract: A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate.Type: ApplicationFiled: September 14, 2012Publication date: March 14, 2013Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Arito Ogawa, Tsuyoshi Takeda
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Patent number: 8367560Abstract: A semiconductor device manufacturing method includes the steps of forming a silicate film by performing a first step of forming a metal oxide film on a silicon substrate, and a second step of inducing a solid phase reaction between the metal oxide film and a surface of the silicon substrate by heat treatment, and forming a high dielectric constant insulating film on the silicate film.Type: GrantFiled: June 10, 2008Date of Patent: February 5, 2013Assignees: Hitachi Kokusai Electric Inc., Rohm Co., Ltd.Inventors: Arito Ogawa, Kunihiko Iwamoto, Hiroyuki Ota
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Publication number: 20120261773Abstract: Disclosed is a semiconductor device that comprises a gate insulating film formed on a semiconductor substrate; a first conductive metal-containing film formed on the gate insulating film; a second conductive metal-containing film, formed on the first metal-containing film, to which aluminum is added; and a silicon film formed on the second metal-containing film.Type: ApplicationFiled: March 21, 2012Publication date: October 18, 2012Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventor: Arito OGAWA
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Publication number: 20110163452Abstract: Provided is a semiconductor device including a metal film which can be formed with lower costs but still mange to have a necessary work function and oxidation resistance. The semiconductor device includes an insulating film disposed on a substrate; and a metal film disposed adjacent to the insulating film. The metal film includes a stacked structure of a first metal film and a second metal film. The oxidation resistance of the first metal film is greater than that of the second metal film. The second metal film has a work function greater than 4.8 eV and is different from the first metal film in material. The first metal film is disposed between the second metal film and the insulating film.Type: ApplicationFiled: January 4, 2011Publication date: July 7, 2011Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Sadayoshi HORII, Arito OGAWA, Hideharu ITATANI
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Patent number: 7884423Abstract: CMISFETs having a symmetrical flat band voltage, the same gate electrode material, and a high permittivity dielectric layer is provided for a semiconductor device including n-MISFETs and p-MISFETs, and a fabrication method thereof, the n-MISFETs including: a first metal oxide layer 20, placed on the 1st gate insulating film 16, having a composition ratio shown with M1xM2yO (where M1=Y, La, Ce, Pr, Nd, Sm, Gd, Th, Dy, Ho, Er, Tm, Yb or Lu, M2=Hf, Zr or Ta, and x/(x+y)>0.12); a second metal oxide layer 24; and a second metal oxide layer 24, the p-MISFETs including: a second gate insulating film 18 placed on the surface of the semiconductor substrate 10; a third metal oxide layer 22, placed on the 2nd gate insulating film 18, having a composition ratio shown with M3zM4wO (M3=Al, M4=Hf, Zr or Ta, and z/(z+w)>0.14); a fourth metal oxide layer 26; and a second conductive layer 30 placed on the fourth metal oxide layer 26.Type: GrantFiled: June 6, 2008Date of Patent: February 8, 2011Assignees: Rohm Co., Ltd., Hitachi Kokusai Electric Inc., Kabushiki Kaisha ToshibaInventors: Kunihiko Iwamoto, Arito Ogawa, Yuuichi Kamimuta
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Publication number: 20110024875Abstract: A high-k capacitor insulating film stable at a higher temperature is formed. There is provided a method of manufacturing a semiconductor device. The method comprises: forming an amorphous first insulating film comprising a first element on a substrate; adding a second element different from the first element to the first insulating film so as to form an amorphous second insulating film on the substrate; and annealing the second insulating film at a predetermined annealing temperature so as to form a third insulating film by changing a phase of the second insulating film. The concentration of the second element added to the first insulating film is controlled according to the annealing temperature.Type: ApplicationFiled: July 30, 2010Publication date: February 3, 2011Applicant: HITACHI-KOKUSAI ELECTRIC INC.Inventors: Yuji TAKEBAYASHI, Hirohisa YAMAZAKI, Sadayoshi Horii, Hideharu ITATANI, Arito OGAWA
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Publication number: 20110003482Abstract: Provided is a method of manufacturing a semiconductor device. In the method, an aluminium-containing insulation film is formed on an electrode film of a substrate by alternately repeating a process of supplying an aluminium precursor into a processing chamber in which the substrate is accommodated and exhausting the aluminium precursor from the processing chamber and a process of supplying an oxidizing or nitriding precursor into the processing chamber and exhausting the oxidizing or nitriding precursor from the processing chamber; and a high permittivity insulation film different from the aluminium-containing insulation film is formed on the aluminium-containing insulation film by alternately repeating a process of supplying a precursor into the processing chamber and exhausting the precursor from the processing chamber and a process of supplying an oxidizing precursor into the processing chamber and exhausting the oxidizing precursor from the processing chamber.Type: ApplicationFiled: June 28, 2010Publication date: January 6, 2011Applicant: HITACHI-KOKUSAI ELECTRIC INC.Inventors: Arito Ogawa, Sadayoshi Horii, Taketoshi SATO, Hideharu Itatani, Nobuyuki MISE, Osamu Tonomura
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Publication number: 20100291763Abstract: Oxidation of a metal film disposed under a high permittivity insulation film can be suppressed, and the productivity of a film-forming process can be improved. In a method of manufacturing a semiconductor device, a first high permittivity insulation film is formed on a substrate by alternately repeating a process of supplying a source into a processing chamber in which the substrate is accommodated and exhausting the source and a process of supplying a first oxidizing source into the processing chamber and exhausting the first oxidizing source; and a second high permittivity insulation film is formed on the first high permittivity insulation film by alternately repeating a process of supplying the source into the processing chamber and exhausting the source and a process of supplying a second oxidizing source different from the first oxidizing source into the processing chamber and exhausting the second oxidizing source.Type: ApplicationFiled: May 17, 2010Publication date: November 18, 2010Applicant: HITACHI-KOKUSAI ELECTRIC INC.Inventors: Arito OGAWA, Sadayoshi Horii, Hideharu ITATANI
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Publication number: 20080318442Abstract: The present invention has an object of providing a substrate processing apparatus and a semiconductor device manufacturing method that can prevent adverse effects on electrical characteristics and provide a thinner EOT. A semiconductor device manufacturing method comprises the steps of: forming a metal oxide film on a silicon substrate, and forming a silicate film by inducing a solid phase reaction between the metal oxide film and the silicon substrate by heat treatment, and forming a high dielectric constant insulating film on the silicate film.Type: ApplicationFiled: June 10, 2008Publication date: December 25, 2008Applicants: HITACHI KOKUSAI ELECTRIC INC., ROHM CO., LTD.Inventors: Arito Ogawa, Kunihiko Iwamoto, Hiroyuki Ota
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Publication number: 20080303099Abstract: CMISFETs having a symmetrical flat band voltage, the same gate electrode material, and a high permittivity dielectric layer is provided for a semiconductor device including n-MISFETs and p-MISFETs, and a fabrication method thereof, the n-MISFETs including: a first metal oxide layer 20, placed on the 1st gate insulating film 16, having a composition ratio shown with M1xM2yO (where M1=Y, La, Ce, Pr, Nd, Sm, Gd, Th, Dy, Ho, Er, Tm, Yb or Lu, M2=Hf, Zr or Ta, and x/(x+y)>0.12); a second metal oxide layer 24; and a second metal oxide layer 24, the p-MISFETs including: a second gate insulating film 18 placed on the surface of the semiconductor substrate 10; a third metal oxide layer 22, placed on the 2nd gate insulating film 18, having a composition ratio shown with M3zM4wO (M3=Al, M4=Hf, Zr or Ta, and z/(z+w)>0.14); a fourth metal oxide layer 26; and a second conductive layer 30 placed on the fourth metal oxide layer 26.Type: ApplicationFiled: June 6, 2008Publication date: December 11, 2008Applicants: Rohm Co., Ltd., Hitachi Kokusai Electric Inc., Kabushiki Kaisha ToshibaInventors: Kunihiko Iwamoto, Arito Ogawa, Yuuichi Kamimuta
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Patent number: 6905928Abstract: When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film is formed, after forming silicon fine particles of particle size 10 nm or less on an oxide film. As a result, it is possible to achieve a high-speed MOS transistor apparatus using an ultra-thin oxide film having a film thickness of 1.5 nm or less, wherein the Ge concentration of the polycrystalline silicon germanium at its interface with the oxide film is uniform, thereby reducing the stress in the film, and improving the reliability of the gate electrode.Type: GrantFiled: May 9, 2002Date of Patent: June 14, 2005Assignee: Hitachi, Ltd.Inventors: Naoki Kanda, Arito Ogawa, Eisuke Nishitani, Miwako Nakahara, Tadanori Yoshida, Kiyoshi Ogata
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Patent number: 6870224Abstract: When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film is formed, after forming silicon fine particles of particle size 10 nm or less on an oxide film. As a result, it is possible to achieve a high-speed MOS transistor apparatus using an ultra-thin oxide film having a film thickness of 1.5 nm or less, wherein the Ge concentration of the polycrystalline silicon germanium at its interface with the oxide film is uniform, thereby reducing the stress in the film, and improving the reliability of the gate electrode.Type: GrantFiled: August 15, 2003Date of Patent: March 22, 2005Assignee: Hitachi, Ltd.Inventors: Naoki Kanda, Arito Ogawa, Eisuke Nishitani, Miwako Nakahara, Tadanori Yoshida, Kiyoshi Ogata
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Publication number: 20040145001Abstract: When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film is formed, after forming silicon fine particles of particle size 10 nm or less on an oxide film. As a result, it is possible to achieve a high-speed MOS transistor apparatus using an ultra-thin oxide film having a film thickness of 1.5 nm or less, wherein the Ge concentration of the polycrystalline silicon germanium at its interface with the oxide film is uniform, thereby reducing the stress in the film, and improving the reliability of the gate electrode.Type: ApplicationFiled: August 15, 2003Publication date: July 29, 2004Applicant: Hitachi, Ltd., IncorporationInventors: Naoki Kanda, Arito Ogawa, Eisuke Nishitani, Miwako Nakahara, Tadanori Yoshida, Kiyoshi Ogata