Patents by Inventor Arkalgud R. Sitaram
Arkalgud R. Sitaram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12113056Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.Type: GrantFiled: December 22, 2022Date of Patent: October 8, 2024Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Cyprian Emeka Uzoh, Arkalgud R. Sitaram, Paul Enquist
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Patent number: 12100684Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.Type: GrantFiled: December 28, 2022Date of Patent: September 24, 2024Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Liang Wang, Rajesh Katkar, Javier A. DeLaCruz, Arkalgud R. Sitaram
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Publication number: 20240145458Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.Type: ApplicationFiled: December 28, 2023Publication date: May 2, 2024Inventors: Cyprian Emeka Uzoh, Arkalgud R. Sitaram, Paul Enquist
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Patent number: 11837596Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.Type: GrantFiled: December 22, 2022Date of Patent: December 5, 2023Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Cyprian Emeka Uzoh, Arkalgud R. Sitaram, Paul Enquist
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Publication number: 20230361072Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.Type: ApplicationFiled: December 28, 2022Publication date: November 9, 2023Inventors: Liang Wang, Rajesh Katkar, Javier A. DeLaCruz, Arkalgud R. Sitaram
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Publication number: 20230317628Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry and a first bonding layer. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over the active circuitry and a second bonding layer on the obstructive material. The second bonding layer can be directly bonded to the first bonding layer without an adhesive. The obstructive material can be configured to obstruct external access to the active circuitry.Type: ApplicationFiled: December 22, 2022Publication date: October 5, 2023Inventors: Belgacem Haba, Javier A. DeLaCruz, Rajesh Katkar, Arkalgud R. Sitaram
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Patent number: 11670615Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.Type: GrantFiled: December 22, 2020Date of Patent: June 6, 2023Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Liang Wang, Rajesh Katkar, Javier A. DeLaCruz, Arkalgud R. Sitaram
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Patent number: 11658173Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.Type: GrantFiled: December 22, 2020Date of Patent: May 23, 2023Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Cyprian Emeka Uzoh, Arkalgud R. Sitaram, Paul Enquist
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Publication number: 20230130580Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.Type: ApplicationFiled: December 22, 2022Publication date: April 27, 2023Inventors: Cyprian Emeka Uzoh, Arkalgud R. Sitaram, Paul Enquist
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Publication number: 20230131849Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.Type: ApplicationFiled: December 22, 2022Publication date: April 27, 2023Inventors: Cyprian Emeka Uzoh, Arkalgud R. Sitaram, Paul Enquist
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Publication number: 20230040454Abstract: Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line.Type: ApplicationFiled: October 4, 2022Publication date: February 9, 2023Inventors: Belgacem Haba, Arkalgud R. Sitaram
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Patent number: 11495579Abstract: Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line.Type: GrantFiled: October 19, 2020Date of Patent: November 8, 2022Assignee: Invensas LLCInventors: Belgacem Haba, Arkalgud R. Sitaram
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Patent number: 11302616Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.Type: GrantFiled: February 28, 2019Date of Patent: April 12, 2022Assignee: Invensas CorporationInventors: Hong Shen, Charles G. Woychik, Arkalgud R. Sitaram, Guilian Gao
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Patent number: 11056390Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.Type: GrantFiled: December 18, 2019Date of Patent: July 6, 2021Assignee: INVENSAS CORPORATIONInventors: Cyprian Emeka Uzoh, Guilian Gao, Liang Wang, Hong Shen, Arkalgud R. Sitaram
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Publication number: 20210202428Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.Type: ApplicationFiled: December 22, 2020Publication date: July 1, 2021Inventors: Liang Wang, Rajesh Katkar, Javier A. DeLaCruz, Arkalgud R. Sitaram
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Publication number: 20210183847Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.Type: ApplicationFiled: December 22, 2020Publication date: June 17, 2021Inventors: Cyprian Emeka Uzoh, Arkalgud R. Sitaram, Paul Enquist
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Publication number: 20210035954Abstract: Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line.Type: ApplicationFiled: October 19, 2020Publication date: February 4, 2021Inventors: Belgacem Haba, Arkalgud R. Sitaram
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Patent number: 10879210Abstract: A bonded structure can include a first element having a first interface feature and a second element having a second interface feature. The first interface feature can be bonded to the second interface feature to define an interface structure. A conductive trace can be disposed in or on the second element. A bond pad can be provided at an upper surface of the first element and in electrical communication with the conductive trace. An integrated device can be coupled to or formed with the first element or the second element.Type: GrantFiled: December 20, 2019Date of Patent: December 29, 2020Assignee: Invensas Bonding Technologies, Inc.Inventors: Paul M. Enquist, Liang Wang, Rajesh Katkar, Javier A. DeLaCruz, Arkalgud R. Sitaram
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Patent number: 10879207Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.Type: GrantFiled: December 20, 2019Date of Patent: December 29, 2020Assignee: Invensas Bonding Technologies, Inc.Inventors: Liang Wang, Rajesh Katkar, Javier A. DeLaCruz, Arkalgud R. Sitaram
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Patent number: 10879226Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.Type: GrantFiled: February 7, 2019Date of Patent: December 29, 2020Assignee: Invensas Bonding Technologies, Inc.Inventors: Cyprian Emeka Uzoh, Arkalgud R. Sitaram, Paul Enquist