Patents by Inventor Arnaud Tournier

Arnaud Tournier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070215909
    Abstract: A pixel having a MOS-type transistor formed in and above a semiconductor substrate of a first doping type, a buried semiconductor layer of a second doping type being placed in the substrate under the MOS transistor and separated therefrom by a substrate portion forming a well. The buried semiconductor layer comprises a thin portion forming a pinch area placed under the transistor channel area and a thick portion placed under all or part of the source/drain areas of the transistor.
    Type: Application
    Filed: March 5, 2007
    Publication date: September 20, 2007
    Applicant: STMicroelectronics S.A.
    Inventors: Arnaud Tournier, Francois Roy
  • Publication number: 20060255371
    Abstract: An integrated circuit includes at least one photodiode associated with a read transistor. The photodiode is formed from a stack of three semiconductor layers comprising a buried layer, an floating substrate layer and an upper layer. The drain region and/or the source region of the transistor are incorporated within the upper layer. The buried layer is electrically isolated from the upper layer so as to allow the buried layer to be biased independently of the upper layer.
    Type: Application
    Filed: May 10, 2006
    Publication date: November 16, 2006
    Applicant: STMicroelectronics S.A.
    Inventors: Francois Roy, Arnaud Tournier
  • Publication number: 20060258042
    Abstract: An integrated circuit includes at least one photodiode of the floating substrate type which is associated with a read transistor. The photodiode is formed from a buried layer lying beneath the floating substrate and an upper layer lying on the floating substrate. The upper layer incorporates the source and drain regions of the read transistor. The source and drain regions are produced on either side of the gate of the read transistor. An isolating trench is located alongside the source region and extends from the upper surface of the upper layer down to below the buried layer, so as to isolate the source region from said buried layer.
    Type: Application
    Filed: May 10, 2006
    Publication date: November 16, 2006
    Applicant: STMicroelectronics S.A.
    Inventors: Francois Roy, Arnaud Tournier
  • Publication number: 20060244090
    Abstract: An integrated circuit includes a photodiode produced from the formation of a stack of three semiconductor layers. An overdoped storage zone is formed in a second (middle) layer of the stack. A read transistor connected to the photodiode includes a gate formed above the stack and source/drain regions formed in a third (upper) layer of the stack. A first (bottom) layer of the stack forms a floating substrate. During integrated circuit fabrication, an implantation mask is placed above the gate and the stack having an opening which exposes a part of the gate and a part of the upper surface of the stack lying beside the exposed part of the gate. An oblique implantation of dopants is then made through the opening in the mask to form the storage zone such that it is at least partially located underneath the gate area of the read transistor.
    Type: Application
    Filed: April 7, 2006
    Publication date: November 2, 2006
    Applicant: STMicroelectronics S.A.
    Inventors: Francois Roy, Arnaud Tournier, Yann Marcellier