Abstract: Various embodiments implementing a multi-fabric mixed-signal electronic system design spanning across multiple design fabrics with electrical and/or thermal analysis awareness. A schematic design may be extracted from and a power delivery network (PDN) model may be determined from a plurality of layouts in multiple design fabrics in a multi-fabric design environment platform. A PDN-aware, multi-fabric full system schematic may be constructed by assembling the PDN model and the schematic design into the PDN-aware, multi-fabric full system schematic. For a schematic generated for a circuit block of interest, chip power models may be determined for the remaining portion of the multi-fabric mixed-signal electronic system design, and the PDN-aware, multi-fabric full system schematic may be updated by accounting for the chip power models. The circuit block of interest may then be electrically and/or thermally analyzed within the context of the remaining portion.

Abstract: Methods and systems of an electronic circuit design system described herein provide a new layout editor tool to make edits in an electronic circuit layout. A plurality of partitions is created in the electronic circuit layout. The new layout editor tool enables multiple electronic circuit designers to edit a different partition of the plurality of partitions of the same electronic circuit layout at the same time and save the edited partition locally.

Abstract: An electronic circuit design system for generating a programmable set of figures of an electronic circuit layout is provided. The system includes a non-transitory machine-readable layout database storing an electronic circuit layout of an electronic circuit design. The system further includes a circuit designer interface for viewing representations of the electronic circuit layout on a display unit and receiving inputs by one or more electronic circuit designers. The system further includes a processor configured to generate a figure group in the electronic circuit layout of the electronic circuit design; generate one or more templates comprising one or more parameters and a programming language code; and generate a parameterized figure group by associating the one or more templates to the figure group.

Abstract: Various embodiments are to a simulation platform with dynamic device model libraries and the implementation therefor. The simulation platform includes one or more servers hosting thereupon a database management system, a simulation frontend, and a simulation backend. The simulation frontend includes or is operatively coupled to one or more electronic design databases managed by a database management system, stored in a persistent storage device, and including design data in one or more domains across one or more design fabrics. The simulation backend includes or is operatively coupled to one or more simulators that perform simulations, analyzes, and/or optimizations for an electronic design by obtaining simulation inputs that are appended to the one or more electronic design databases or are stored in one or more separate data structures that are co-managed by the database management system.

Abstract: Disclosed are techniques for implementing electronic design layouts with symbolic representations. These techniques determine an abstraction scope of a layout circuit component in a layout of an electronic design by referencing a user input or one or more default settings of the abstraction mechanism and identify first data that are included in or associated with a schematic symbol for the layout circuit component by traversing data from a symbolic representation data source with reference to the abstraction scope with the layout editing mechanism. In addition, these techniques further generate a symbolic representation for the layout circuit component by reproducing at least some of the first data in the layout and perform one or more layout operations on the symbolic representation to improve the layout and to generate a result set for the one or more layout operations.

Abstract: A system and method are provided for accelerated graphic rendering a view of a design layout view represented by a plurality of graphic objects defined by respective geometry data therefor. A database stores the geometry data having location and geometric portions. A large object module actuates retrieval of the geometry data for each of the graphic objects within the view selectively classified to be a large object. A small object module actuates partial retrieval of the geometry data for each of the graphic objects within the view selectively classified to be a small object, the location portion being thereby retrieved exclusive of the geometric portion of the geometry data for each small object. A rendering control module generates a composite image of the design layout view for display, which includes a geometric reproduction of each large object and an abstracted representation of each small object within the view.

Abstract: Various embodiments implement multi-fabric designs by using respective EDA tools associated with multiple design fabrics to access their respective native design data. Each EDA tool has access to and processes or manipulates its corresponding native design data; and no EDA tools have the visibility of the entire multi-fabric electronic design. Requests for actions are automatically transmitted among these EDA tools to instantiate desired EDA tools and to descend or ascend the multi-fabric design structure so that native design data in a particular design fabric are processed by the corresponding EDA tool(s) within the context of the other design fabrics. These techniques enable designers to implement, check, verify, simulate, analyze, probe, and netlist the entire electronic design across multiple design fabric.

Abstract: Described are methods and systems for netlisting or probing multi-fabric designs that identify a request for process at least a portion of a multi-fabric electronic design and determine a first partial listing of one or more first circuit components in response to the request by at least identifying first design data in a first design fabric of the one or more first circuit components using a first session of a first electronic design automation (EDA) tool. The methods and systems further automatically transmit a request for action related to the one or more first circuit components from the first session to a second session of a second EDA tool and determine a second partial listing of one or more second circuit components by at least identifying second design data in a second design fabric of the one or more second circuit components using the second session.

Abstract: Disclosed are techniques to analyze multi-fabric designs. These techniques generate a cross-fabric analysis model by at least identifying first design data in a first design fabric of a multi-fabric electronic design using a first session of a first electronic design automation (EDA) tool, update the cross-fabric simulation model by at least identifying second design data in a second design fabric using a second session of a second EDA tool, and determine analysis results for the multi-fabric electronic design using at least the cross-fabric simulation model. Analysis results may be determined using parasitic, electrical, or performance information.

Abstract: Disclosed are various techniques that check, verify, or test multi-fabric designs by receiving a request for checking correctness of a multi-fabric design across at least a first design fabric and a second design fabric. A request for action is transmitted from a first EDA tool session to a second EDA tool session. Connectivity information of second design data in the second design fabric is identified by the second EDA tool session in response to the request for action from the first EDA tool session. These various techniques then check the correctness of the multi-fabric design in the first design fabric by using at least the connectivity information of the second design data. A symbolic representation may be used to represent design data in an EDA tool session to which the design data are not native.

Abstract: A method identifying an element in a document corresponding to an edit selected from a list of available edits to distinguish the selected edit from the other edits in the list. The identifying may reflect the type of edit, or otherwise demonstrate the change to the element effectuated by the edit. Multiple edits may be selected and temporarily highlighted or otherwise identified in chronological order to demonstrate the effect of multiple edits on the elements of the document.

Abstract: A system and method for enabling the display and movement of a boundary box of an instance master inclusive of specific predetermined geometric figures, including master pins, master halo and master boundary edges, is provided. The system and method provides for improved utilization of computer resources and enables users of the present invention to be able to drag and use instance master in their designs more efficiently and rapidly.

Abstract: A system and method for synchronizing the display and edit of a plurality of connected layouts or documents within a single display. A first document or plurality of elements may be displayed as active and a second document or plurality of elements may be displayed as non-active background in a first window. The second document or plurality of elements may be displayed as active and the first document or plurality of elements may be displayed as non-active background in a second window. Any action detected in either window may be displayed in the other window. Upon selection of any active element or predefined net list, the elements physically or logically connected to the selected element or net list may be highlighted in the active documents, listed, or otherwise identified. An inter-document net list may identify connections between existing net lists in multiple documents.

Abstract: The subject system and method are generally directed to the user-friendly insertion of at least one device, and optionally chains of devices, into at least one pre-existing chain of interconnected devices within a graphical representation of a circuit design such as a circuit layout, circuit mask, or a schematic. The system and method provide for discerning the intended insertion points and performing remedial transformations of the devices within the chains to ensure compliance with both structural and operational requirements of the circuit design.

Abstract: A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.

Abstract: Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic.

Abstract: Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic.

Abstract: A method is provided to align poly features within chain sets in an integrated circuit layout design stored in a non-transitory computer readable storage device comprising: vertically aligning a first poly feature of a first pcell instance in a first chain set with a second poly feature of a second pcell instance in a second chain set; configuring a computer to, starting with the aligned first and second poly features, successively determine multiple changed poly feature spacing values associated with at least one of the first and second pcell instances to align successive poly features in chain order in a first horizontal direction; and assigning respective determined changed poly feature spacing values to their associated first or second pcell instances.

Abstract: A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.

Abstract: In one embodiment of the invention, a method of analyzing a circuit design is disclosed. In the method of analyzing a circuit design, a circuit is levelized into multiple levels. Circuit simulations of elements at a level are determined using circuit simulators, one for each element and in parallel in level order. Topological circuit loops may be removed from the circuit. Circuit simulation of the circuit may be performed on the circuit using the circuit simulations determined by the circuit simulators at each level of the circuit.