Abstract: A system and method for synchronizing the display and edit of a plurality of connected layouts or documents within a single display. A first document or plurality of elements may be displayed as active and a second document or plurality of elements may be displayed as non-active background in a first window. The second document or plurality of elements may be displayed as active and the first document or plurality of elements may be displayed as non-active background in a second window. Any action detected in either window may be displayed in the other window. According to an embodiment, the layouts or documents may be connected via an interposer.

Abstract: A system and method for synchronizing the display and edit of a plurality of connected layouts or documents within a single display. A first document or plurality of elements may be displayed as active and a second document or plurality of elements may be displayed as non-active background in a first window. The second document or plurality of elements may be displayed as active and the first document or plurality of elements may be displayed as non-active background in a second window. Any action detected in either window may be displayed in the other window. Upon selection of any active element or predefined net list, the elements physically or logically connected to the selected element or net list may be highlighted in the active documents, listed, or otherwise identified. An inter-document net list may identify connections between existing net lists in multiple documents.

Abstract: Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design.

Abstract: A method and an apparatus are described for allowing several different applications to incrementally collaborate while making changes to a circuit design.

Abstract: An improved approach to pcell caching is disclosed that enables safe and efficient multi-user access to pcell caches. Locking structures are used in conjunction with counters to provide multi-user support for pcell caches. When a modification occurs to cached pcell data, an update is made to the appropriate counter(s). The value(s) of the counters are checked to determine whether the item of data operated upon by an entity is still valid or if another concurrent entity has made changes to the data.

Abstract: Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design.

Abstract: A method is provided to produce an integrated circuit layout design comprising: providing in non-transitory storage a pPar parent cell that includes one or more pPar instances and that specifies one or more corresponding input parameter values; producing a graphical representation on a computer display screen of a first schematic design that includes a pPar parent instance; instantiating in non-transitory storage a parameterized cell supermaster that corresponds to the pPar parent cell; determining whether a core layout cell is stored in non-transitory storage that corresponds to the parameterized cell supermaster and the one or more corresponding input parameter values; in response to determining that such a core layout cell is stored, filling a first parameterized cell submaster with an instance of the stored core layout cell; in response to determining that such a core layout cell is not stored, using program code associated with the parameterized cell supermaster to generate a core layout cell; and storin

Abstract: The present invention provides a method for generating flat layout design view that comprises importing port definitions of a first hierarchical block of digital instances from a source as a schematic symbol, importing port definitions of digital instances within the first hierarchical block from the source, instantiating the schematic symbol as a hierarchical layout instance in the flat layout, binding the hierarchical layout instance to the schematic symbol, and embedding digital layout block instances within the design layout by replacing the digital instances of a digital layout block with digital layout instances of a top layout module of the design layout.

Abstract: A method identifying an element in a document corresponding to an edit selected from a list of available edits to distinguish the selected edit from the other edits in the list. The identifying may reflect the type of edit, or otherwise demonstrate the change to the element effectuated by the edit. Multiple edits may be selected and temporarily highlighted or otherwise identified in chronological order to demonstrate the effect of multiple edits on the elements of the document.

Abstract: Systems and methods to enable a user to edit subMaster content of selected instances of an electronic layout design, including editing the contents of selected instances of an existing subMaster of an EDA design, generating a new subMaster to incorporate the modified contents of the selected instances, and binding the new subMaster to the selected instances without losing the design hierarchy of the layout design.

Abstract: Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic.

Abstract: Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic.

Abstract: Techniques are present for designing of integrated circuits. Both custom design data and synthesized digital design data are received and merged into a design database in an automated process. The design database is then made accessible to layout tools so that the layout tools may operate upon it. These layout tools can include, but are not limited to, custom tools, digitals, or a combinations of these.

Abstract: Parameterized cells are cached and provided by the plug-in to increase the speed and efficiency of an application for circuit design. This allows source design to be read-interoperable and also enables some basic write-interoperability in the source design.

Abstract: An improved method and system are disclosed for utilizing abstracted versions of layout portions in conjunction with parameterized cells (pcells). One significant advantage is that abstracted versions of pcells can be generated from normal pcells and stored in a pcell cache, which avoids the need to abstract layout pcells on the fly.

Abstract: Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design.

Abstract: The present invention provides a method for generating flat layout design view that comprises importing port definitions of a first hierarchical block of digital instances from a source as a schematic symbol, importing port definitions of digital instances within the first hierarchical block from the source, instantiating the schematic symbol as a hierarchical layout instance in the flat layout, binding the hierarchical layout instance to the schematic symbol, and embedding digital layout block instances within the design layout by replacing the digital instances of a digital layout block with digital layout instances of a top layout module of the design layout.

Abstract: An improved approach to pcell caching is disclosed that enables safe and efficient multi-user access to pcell caches. Locking structures are used in conjunction with counters to provide multi-user support for pcell caches. When a modification occurs to cached pcell data, an update is made to the appropriate counters). The value(s) of the counters are checked to determine whether the item of data operated upon by an entity is still valid or if another concurrent entity has made changes to the data.

Abstract: Method for updating a circuit design. A modification to a netlist that includes original components and original spare cells is received. Original components that are not required by the modification are identified, disconnected and marked or made new spare cells. A pool of spare cells is generated and includes original and new spare cells. The netlist is updated by adding new components, and added components are mapped to spare cells selected from the pool. If mapping does not satisfy a design constraint, such as a timing constraint, then original components can be de-mapped and made spare cells, added components are mapped to spare cells resulting from de-mapping, and de-mapped components can be re-mapped to other spare cells.

Abstract: A method and system for maintaining synchronization between a plurality of layout clones of an integrated circuit design, wherein each layout clone comprises at least one figure. The method comprises tracking relationships between equivalent figures of the plurality of layout clones, wherein the plurality of layout clones are associated with one another within an equivalence group and propagating an edit made in one of the layout clones within an equivalence group to the other layout clones within the equivalence group.