Abstract: An information handling system includes dock and compute portions. The dock portion communicates with a peripheral device. The compute portion includes an external communication port and a processor. The processor determines whether an external information handling system is connected to the external communication port. In response to the external information handling system being connected to the external communication port, the processor enters the information handling system into a dock operating mode. While in the dock operating mode commands from the external information handling system are provided from the external communication port, through the dock portion, and to the peripheral device. In response to the external information handling system not being connected to the external communication port, the processor enters the information handling system into a compute operating mode.

Abstract: In auto-configuration of dense mesh networks an Information Handling System (IHS) runs an advertisement service when the IHS is powered on and transmits a wireless local area network beacon information element that includes wireless node IHS specific information. The IHS dynamically scales transmit power of advertisement packets, from a low power. In response to the IHS finding a cluster host, the IHS accepts configuration of the IHS with an identification for a cluster of the cluster host and a frequency channel within the cluster. In response to the IHS not finding a cluster host, the IHS identifies as a new (cluster) host IHS and defines an identification for the new cluster. The cluster identification may be a Basic Secure Set (BSS) color field of the information element. Defining the identification for a cluster may use a distributed cluster policy, or may use a centralized managed cluster policy.

Abstract: Information handling system (IHS) heatsinking systems and methods may employ a thermally conductive compression attached memory module (CAMM) bolster plate affixed to one surface of a circuit board of the CAMM, between a central processing unit (CPU) of the IHS and memory devices mounted on the CAMM, to provide compression between the CAMM and a z-axis compression connector and to capture and dissipate heat from the CPU and the memory devices. Spacing between the CPU and the DIMM may enable this capture and dissipation of heat from the CPU. The bolster plate may be configured to receive at least one conductive fastener that bears on the bolster plate and presses the CAMM to the z-axis compression connector, and to conductively thermally couple the CAMM and bolster plate to a ground plane of a system printed circuit board (PCB) mounting the CPU and the CAMM.

Abstract: A memory module mounting apparatus for coupling a memory module to a processor of an information handling system includes a z-axis compression connector and a compression connector mount. The z-axis compression connector has first compression contacts on a first surface of the compression connector and second compression contacts on a second surface of the compression connector. The first compression contacts couple the compression connector to the processor. The compression connector mount has contact pads on a first surface of the compression connector mount. The first contact pads couple the compression connector mount to the first compression contacts, and have contact elements configured to couple the contact pads to the memory module.

Abstract: Embodiments of systems and methods for a Compression Attached Memory Module (CAMM) for Low-Power Double Data Rate (LPDDR) memories are described. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include: a compression Dual In-Line Memory Module (cDIMM) connector coupled to a motherboard; and a memory module coupled to the cDIMM connector, where the memory module comprises an LPDDR device coupled to a top surface of the memory module and accessible via surface contact connections disposed on a bottom surface of the memory module.

Abstract: An information handling system includes a first z-axis compression connector having a first depth, a first memory module, a second z-axis compression connector having a second depth that is greater than the first depth, a second memory module, and a printed circuit board. A first side of the first compression connector is affixed to the printed circuit board at a first location and a first surface of a first memory circuit board of the first memory module is affixed to a second side of the first compression connector. A first side of the second compression connector is affixed to the printed circuit board at a second location adjacent to the first location and the first side of a second memory circuit board of the second memory module is affixed to a second side of the second compression connector.

Abstract: An information handling system includes a first z-axis compression connector having a first depth, a first memory module, a second z-axis compression connector having a second depth that is greater than the first depth, a second memory module, and a printed circuit board. A first side of the first compression connector is affixed to the printed circuit board at a first location and a first surface of a first memory circuit board of the first memory module is affixed to a second side of the first compression connector. A first side of the second compression connector is affixed to the printed circuit board at a second location adjacent to the first location and the first side of a second memory circuit board of the second memory module is affixed to a second side of the second compression connector.

Abstract: A holder for stacked compression attached memory modules (CAMMs) includes an outer frame, a first recessed area for receiving a bottom one of the stacked CAMMs, a second recessed area for receiving a top one of the stacked CAMMs, and a metal plate assembly affixed within the outer frame and situated between the first recessed area and the second recessed area.

Abstract: Implementing interference avoidance for high density ad hoc networks may include creating ad hoc Wireless Local Area Network (WLAN) clusters (WLAN pico-nets) of Information Handling Systems (IHSs) with nonoverlapping channels, enabling each IHS to have a high bandwidth wireless interface, and isolating nearby ad hoc WLAN clusters, using a Basic Secure Set (BSS) color field to associate IHSs within an ad hoc WLAN cluster (which may be preconfigured for each ad hoc WLAN cluster). Physical separation of ad hoc WLAN clusters may be optimized, minimizing cochannel interference, such as through use of dynamic threshold calculations. Nearby ad hoc WLAN clusters may be further isolated by dynamically adjusting transmit power control to isolate nearby ad hoc WLAN clusters, and/or by scaling channel width, such as through Dynamic Throughput Scalar calculations.

Abstract: A z-axis compression connector includes a plurality of high-speed signal contacts arranged in a grid of M rows by N columns, and a plurality of signal return contacts arranged between the N columns. A first signal return contact is positioned mid-way in line between a first signal contact and a second signal contact, where the first signal contact is in a first row and a first column and the second signal contact is in the first row and a second column adjacent to the first column.

Abstract: A holder for a compression attached memory module (CAMM) includes a spine and first and second beam protrusions. The spine encloses an end of the CAMM adjacent to a contact pad array of a CAMM printed circuit board (PCB) of the CAMM. The first beam protrusion extends from the spine away from the end of the CAMM. The second beam protrusion extends from the spine away from the end of the CAMM. When the CAMM is installed into the holder and installed into an information handling system, the first and second beam protrusions transfer a compression applied at the first and a compression applied at the second beam protrusions to a portion of the spine between the first beam protrusion and the second beam protrusion to limit a deformation of the CAMM PCB.

Abstract: A z-axis compression connector includes a plurality of high-speed signal contacts arranged in a grid of M rows by N columns, and a plurality of signal return contacts arranged between the N columns. A first signal return contact is positioned mid-way in line between a first signal contact and a second signal contact, where the first signal contact is in a first row and a first column and the second signal contact is in the first row and a second column adjacent to the first column.

Abstract: A system may include a circuit board comprising a inductor coil formed in a circuit board around a hole formed through the circuit board and a presence detection subsystem configured to measure an electrical quantity occurring within the inductor coil responsive to an alternating current driven to the inductor coil and determine whether an object is present within the hole based on the electrical quantity.

Abstract: An edge connector for coplanar coupling of two printed circuit boards (PCBs) comprises an elongated body and two end structures. The elongated body has a compression contact space and two PCB contact surfaces, each PCB contact surface having a plurality of contact positions. Portions of compression contacts positioned in the compression contact space extend through contact positions on both PCB contact surfaces. When a PCB edge surface contacts a PCB contact surface of the elongated body, an edge connection on the PCB edge surface contacts a compression contact, forming an electrical connection. Each end structure has two contact pairs, wherein each contact pair has attaching features that couple the edge connector to a PCB to maintain the electrical connection. When two PCBs are coupled to the edge connector, the compression contacts form electric paths for conducting power and/or communication between the two PCBs.

Abstract: Ranks of one or more memory modules can have variable data widths. As part of initializing a memory architecture, a memory controller can be configured to detect the data width of the ranks in the memory architecture. Based on the detected data widths of the ranks, the memory controller can synchronize the clocks and chip select signals of multiple ranks to thereby cause one or more memory chips in each of the multiple ranks to be connected to the shared data lines at the same time.

Abstract: Removeable couplings are provided for connecting a memory module to a host processor of an IHS (Information Handling System). The coupling includes electrical contacts and fasteners for positioning the electrical contacts within an empty memory slot of the IHS motherboard. The housing extends between two ends of the coupling and receives the memory module when the memory module is installed in the IHS. The positioned electrical contacts are then seated within the memory slot of the motherboard by the downward force applied by an administrator in installing the memory module to the coupling. The force applied in installing the memory module also serves to connect the electrical contacts of the coupling to a memory channel of the motherboard. The removeable coupling is not attached to the motherboard when the memory module is not installed in the IHS, thus eliminating signal stubs in the memory channel.

Abstract: A memory module includes a printed circuit board and a Low-Power Double Data Rate (LPDDR) memory device. The printed circuit board includes surface contact connections on a first surface of the printed circuit board and located at a first portion of the printed circuit board. The LPDDR memory device is on a second surface of the printed circuit board and located at a second portion of the printed circuit board. The LPDDR memory device is configured to be coupled to an information handling system via the surface contact connections. The second portion of the printed circuit board is adjacent to the first portion of the printed circuit board.

Abstract: Embodiments of systems and methods for a Compression Attached Memory Module (CAMM) for Low-Power Double Data Rate (LPDDR) memories are described. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include: a compression Dual In-Line Memory Module (cDIMM) connector coupled to a motherboard; and a memory module coupled to the cDIMM connector, where the memory module comprises an LPDDR device coupled to a top surface of the memory module and accessible via surface contact connections disposed on a bottom surface of the memory module.

Abstract: An edge connector for coplanar coupling of two printed circuit boards (PCBs) comprises an elongated body and two end structures. The elongated body has a compression contact space and two PCB contact surfaces, each PCB contact surface having a plurality of contact positions. Portions of compression contacts positioned in the compression contact space extend through contact positions on both PCB contact surfaces. When a PCB edge surface contacts a PCB contact surface of the elongated body, an edge connection on the PCB edge surface contacts a compression contact, forming an electrical connection. Each end structure has two contact pairs, wherein each contact pair has attaching features that couple the edge connector to a PCB to maintain the electrical connection. When two PCBs are coupled to the edge connector, the compression contacts form electric paths for conducting power and/or communication between the two PCBs.

Abstract: An information handling system includes a first z-axis compression connector, a first dual in-line memory module (DIMM), a second z-axis compression connector, a second DIMM, and a printed circuit board. A first side of the first compression connector is affixed to the printed circuit board. A first surface of a first memory circuit board of the first DIMM is affixed to a second side of the compression connector. A first side of the second compression connector is affixed to a second side of the first memory circuit board. A first side of a second memory circuit board of the second DIMM is affixed to a second side of the second compression connector. The first compression connector has a first depth, and the second compression connector has a second depth that is different from the first depth.