Abstract: A system and method of implementing an adaptable graphics board form factor design comprising an adaptable graphics board including a reconfigurable zone subset of components including a reconfigurable I/O module having display data ports disposed along a first edge of the adaptable graphics board, the adaptable graphics board including a set of core components including the graphics processor and graphics memory, wherein the reconfigurable zone subset of components are orientable relative to the set of core components to interface with an information handling system chassis of a first model specification selected from a plurality of model specifications for information handling systems in which the adaptable graphics board may be used, and the adaptable graphics board including a connector pad interface area for receiving an array of compressible electrical spring contacts of a compression jumper pad for a flexible compression jumper connector, wherein the connector pad interface area is disposed along a sec

Abstract: A system and method of implementing an adaptable graphics board comprising the adaptable graphics board including a graphics processor, graphics memory, and a reconfigurable I/O module interface are having a plurality of electrical contacts, a dual compression connector having a first array of compressible electrical spring contacts on a first side and a second array of compressible electrical spring contacts on a second side operatively coupled to the first side via a dual compression connector printed circuit board layer, the first side of the dual compression connector operatively coupled to the reconfigurable I/O module interface of the adaptable graphics board, and a reconfigurable I/O module board having external display data ports disposed along an edge, wherein the reconfigurable I/O module board is operatively coupled to the adaptable graphics board via the second side of the dual compression connector.

Abstract: In some implementations a logic device, such as an embedded controller, automatically configures a universal serial bus (USB) Type-C port by connecting the USB Type-C port to appropriate input/output (I/O) signals. For example, the logic device may receive a notification that an external device is connected to a USB Type-C port of a computing device. The logic device may receive data from a port controller over an internal communication bus associated with the USB Type-C port. Based at least in part on the data, the logic device may determine one or more types of signals that the external device is configured to send, receive, or send and receive. The logic device may instruct a cross-point switch to connect the USB Type-C port to one or more signal paths in the computing device to enable the external device to send/receive the one or more types of signals.

Abstract: In some implementations a logic device, such as an embedded controller, automatically configures a universal serial bus (USB) Type-C port by connecting the USB Type-C port to appropriate input/output (I/O) signals. For example, the logic device may receive a notification that an external device is connected to a USB Type-C port of a computing device. The logic device may receive data from a port controller over an internal communication bus associated with the USB Type-C port. Based at least in part on the data, the logic device may determine one or more types of signals that the external device is configured to send, receive, or send and receive. The logic device may instruct a cross-point switch to connect the USB Type-C port to one or more signal paths in the computing device to enable the external device to send/receive the one or more types of signals.

Abstract: A system and method of implementing an adaptable graphics board form factor design comprising an adaptable graphics board including a reconfigurable zone subset of components including a reconfigurable I/O module having display data ports disposed along a first edge of the adaptable graphics board, the adaptable graphics board including a set of core components including the graphics processor and graphics memory, wherein the reconfigurable zone subset of components are orientable relative to the set of core components to interface with an information handling system chassis of a first model specification selected from a plurality of model specifications for information handling systems in which the adaptable graphics board may be used, and the adaptable graphics board including a connector pad interface area for receiving an array of compressible electrical spring contacts of a compression jumper pad for a flexible compression jumper connector, wherein the connector pad interface area is disposed along a sec

Abstract: A computing device may include a universal serial bus (USB) port, a port controller, and a first port multiplexer. The port controller may determine that a connector of a cable has been connected to the port of the computing device and determine that the cable includes a second port multiplexer. The port controller may send a first instruction to the first port multiplexer to select a single-ended signaling configuration and send a second instruction to the second port multiplexer to select the single-ended signaling configuration. In the single-ended configuration, the first port multiplexer may receive a set of differential signals, convert the set of differential signals to a corresponding set of single-ended signals, and output the set of single-ended signals to the port.

Abstract: A system and method for provisioning within a system design to allow the storage and IO resources to scale with compute resources are provided.

Abstract: A system for a system and method for provisioning of modular compute resources within a system design are provided.

Abstract: A GPU can be configured to selectively function as a PCIe switch so that a PCIe link can be formed between the GPU and a remote GPU. The GPU can include a DisplayPort interface that is coupled via a multiplexer to a USB type-C port. When it is desired to implement remote graphics, the GPU can cause the DisplayPort interface to instead function as a PCIe interface between the GPU and the multiplexer. With this PCIe connection, the GPU can forward its PCIe interface with the CPU to the remote GPU via the USB type-C port. In this way, remote graphics can be implemented without using Thunderbolt to tunnel the PCIe interface to the remote GPU.

Abstract: A GPU can be configured to selectively function as a PCIe switch so that a PCIe link can be formed between the GPU and a remote GPU. The GPU can include a DisplayPort interface that is coupled via a multiplexer to a USB type-C port. When it is desired to implement remote graphics, the GPU can cause the DisplayPort interface to instead function as a PCIe interface between the GPU and the multiplexer. With this PCIe connection, the GPU can forward its PCIe interface with the CPU to the remote GPU via the USB type-C port. In this way, remote graphics can be implemented without using Thunderbolt to tunnel the PCIe interface to the remote GPU.

Abstract: In some implementations a logic device, such as an embedded controller, automatically configures a universal serial bus (USB) Type-C port by connecting the USB Type-C port to appropriate input/output (I/O) signals. For example, the logic device may receive a notification that an external device is connected to a USB Type-C port of a computing device. The logic device may receive data from a port controller over an internal communication bus associated with the USB Type-C port. Based at least in part on the data, the logic device may determine one or more types of signals that the external device is configured to send, receive, or send and receive. The logic device may instruct a cross-point switch to connect the USB Type-C port to one or more signal paths in the computing device to enable the external device to send/receive the one or more types of signals.

Abstract: A system and method for provisioning of modular compute resources within a system design are provided. In one embodiment, a node card or a system board may be used.

Abstract: A system and method for provisioning within a system design to allow the storage and IO resources to scale with compute resources are provided.

Abstract: A server on a chip that can be a component of a node card. The server on a chip can include a node central processing unit subsystem, a peripheral subsystem, a system interconnect subsystem, and a management subsystem. The central processing unit subsystem can include a plurality of processing cores each running an independent instance of an operating system. The peripheral subsystem includes a plurality of interfaces for various configurations of storage media. The system interconnect subsystem provides for intra-node and inter-node packet connectivity. The management subsystem provides for various system and power management functionalities within the subsystems of the server on a chip.

Abstract: A system and method for provisioning within a system design to allow the storage and IO resources to scale with compute resources are provided.

Abstract: A computing device may include a universal serial bus (USB) port, a port controller, and a first port multiplexer. The port controller may determine that a connector of a cable has been connected to the port of the computing device and determine that the cable includes a second port multiplexer. The port controller may send a first instruction to the first port multiplexer to select a single-ended signaling configuration and send a second instruction to the second port multiplexer to select the single-ended signaling configuration. In the single-ended configuration, the first port multiplexer may receive a set of differential signals, convert the set of differential signals to a corresponding set of single-ended signals, and output the set of single-ended signals to the port.

Abstract: A server on a chip that can be a component of a node card. The server on a chip can include a node central processing unit subsystem, a peripheral subsystem, a system interconnect subsystem, and a management subsystem. The central processing unit subsystem can include a plurality of processing cores each running an independent instance of an operating system. The peripheral subsystem includes a plurality of interfaces for various configurations of storage media. The system interconnect subsystem provides for intra-node and inter-node packet connectivity. The management subsystem provides for various system and power management functionalities within the subsystems of the server on a chip.

Abstract: A server on a chip that can be a component of a node card. The server on a chip can include a node central processing unit subsystem, a peripheral subsystem, a system interconnect subsystem, and a management subsystem. The central processing unit subsystem can include a plurality of processing cores each running an independent instance of an operating system. The peripheral subsystem includes a plurality of interfaces for various configurations of storage media. The system interconnect subsystem provides for intra-node and inter-node packet connectivity. The management subsystem provides for various system and power management functionalities within the subsystems of the server on a chip.

Abstract: A system for a system and method for provisioning of modular compute resources within a system design are provided.

Abstract: A system and method for provisioning of modular compute resources within a system design are provided. In one embodiment, a node card or a system board may be used.