Abstract: A method for manufacturing a bipolar punch-through semiconductor device is disclosed, which includes providing a wafer having a first and a second side, wherein on the first side a high-doped layer of the first conductivity type having constant high doping concentration is arranged; epitaxially growing a low-doped layer of the first conductivity type on the first side; performing a diffusion step by which a diffused inter-space region is created at the inter-space of the layers; creating at least one layer of the second conductivity type on the first side; and reducing the wafer thickness within the high-doped layer on the second side so that a buffer layer is created, which can include the inter-space region and the remaining part of the high-doped layer, wherein the doping profile of the buffer layer decreases steadily from the doping concentration of the high-doped region to the doping concentration of the drift layer.

Abstract: A bipolar punch-through semiconductor device has a semiconductor substrate, which includes at least a two-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact. One of the layers in the two-layer structure is a base layer of the first conductivity type. A buffer layer of the first conductivity type is arranged on the base layer. A first layer includes alternating first regions of the first conductivity type and second regions of the second conductivity type. The first layer is arranged between the buffer layer and the second electrical contact. The second regions are activated regions with a depth of at maximum 2 ?m and a doping profile, which drops from 90% to 10% of the maximum doping concentration within at most 1 ?m.

Abstract: In order to produce a power semiconductor for operation at high blocking voltages, there is produced on a lightly doped layer having a doping of a first charge carrier type a medium-doped layer of the same charge carrier type. A highly doped layer is produced at that side of the medium-doped layer which is remote from the lightly doped layer, of which highly doped layer a part with high doping that remains in the finished semiconductor forms a second stop layer, wherein the doping of the highly doped layer is higher than the doping of the medium-doped layer. An electrode is subsequently indiffused into the highly doped layer. The part with low doping that remains in the finished semiconductor forms the drift layer and the remaining medium-doped part forms the first stop layer.

Abstract: A reverse-conducting semiconductor device includes a freewheeling diode and an insulated gate bipolar transistor (IGBT) on a common wafer. Part of the wafer forms a base layer with a base layer thickness. The IGBT includes a collector side and an emitter side arranged on opposite sides of the wafer. A first layer of a first conductivity type and a second layer of a second conductivity type are alternately arranged on the collector side. The first layer includes at least one first region with a first region width and at least one first pilot region with a first pilot region width. The second layer includes at least one second region with a second region width and at least one second pilot region with a second pilot region width. Each second region width is equal to or larger than the base layer thickness, whereas each first region width is smaller than the base layer thickness. Each second pilot region width is larger than each first pilot region width.

Abstract: A controlled-punch-through semiconductor device with a four-layer structure is disclosed which includes layers of different conductivity types, a collector on a collector side, and an emitter on an emitter side which lies opposite the collector side. The semiconductor device can be produced by a method performed in the following order: producing layers on the emitter side of wafer of a first conductivity type; thinning the wafer on a second side; applying particles of the first conductivity type to the wafer on the collector side for forming a first buffer layer having a first peak doping concentration in a first depth, which is higher than doping of the wafer; applying particles of a second conductivity type to the wafer on the second side for forming a collector layer on the collector side; and forming a collector metallization on the second side.

Abstract: A reverse-conducting insulated gate bipolar transistor includes a wafer of first conductivity type with a second layer of a second conductivity type and a third layer of the first conductivity type. A fifth electrically insulating layer partially covers these layers. An electrically conductive fourth layer is electrically insulated from the wafer by the fifth layer. The third through the fifth layers form a first opening above the second layer. A sixth layer of the second conductivity type and a seventh layer of the first conductivity type are arranged alternately in a plane on a second side of the wafer. A ninth layer is formed by implantation of ions through the first opening using the fourth and fifth layers as a first mask.

Abstract: A power semiconductor device, such as a power diode, and a method for producing such a device, are disclosed. The device includes a first layer of a first conductivity type, a second layer of a second conductivity type arranged in a central region on a first main side of the first layer, a third electrically conductive layer arranged on the second layer, and a fourth electrically conductive layer arranged on the first layer at a second main side opposite to the first main side. A junction termination region surrounds the second layer with self-contained sub-regions of the second conductivity type. A spacer region is arranged between the second layer and the junction termination region and includes a self-contained spacer sub-region of the second conductivity type which is electrically disconnected from the second layer.

Abstract: A power semiconductor device is disclosed with layers of different conductivity types between an emitter electrode on an emitter side and a collector electrode on a collector side. The device can include a drift layer, a first base layer in direct electrical contact to the emitter electrode, a first source region embedded into the first base layer which contacts the emitter electrode and has a higher doping concentration than the drift layer, a first gate electrode in a same plane and lateral to the first base layer, a second base layer in the same plane and lateral to the first base layer, a second gate electrode on top of the emitter side, and a second source region electrically insulated from the second base layer, the second source region and the drift layer by a second insulating layer.

Abstract: A method of manufacturing a power semiconductor device is provided. A first oxide layer is produced on a first main side of a substrate of a first conductivity type. A structured gate electrode layer with at least one opening is then formed on the first main side on top of the first oxide layer. A first dopant of the first conductivity type is implanted into the substrate on the first main side using the structured gate electrode layer as a mask, and the first dopant is diffused into the substrate. A second dopant of a second conductivity type is then implanted into the substrate on the first main side, and the second dopant is diffused into the substrate. After diffusing the first dopant into the substrate and before implanting the second dopant into the substrate, the first oxide layer is partially removed. The structured gate electrode layer can be used as a mask for implanting the second dopant.

Abstract: A maximum-punch-through semiconductor device such as an insulated gate bipolar transistor (IGBT) or a diode, and a method for producing same are disclosed. The MPT semiconductor device can include at least a two-layer structure having an emitter metallization, a channel region, a base layer with a predetermined doping concentration ND, a buffer layer and a collector metallization. A thickness W of the base layer can be determined by: W = V bd + V pt 4010 ? ? kV ? ? cm - 5 / 8 * ( N D ) 1 / 8 wherein a punch-through voltage Vpt of the semiconductor device is between 70% and 99% of a break down voltage Vbd of the semiconductor device, and wherein the thickness W is a minimum thickness of the base layer between a junction to the channel region and the buffer layer.

Abstract: A reverse-conducting semiconductor device is disclosed with an electrically active region, which includes a freewheeling diode and an insulated gate bipolar transistor on a common wafer. Part of the wafer forms a base layer with a base layer thickness. A first layer of a first conductivity type with at least one first region and a second layer of a second conductivity type with at least one second and third region are alternately arranged on the collector side. Each region has a region area with a region width surrounded by a region border. The RC-IGBT can be configured such that the following exemplary geometrical rules are fulfilled: each third region area is an area, in which any two first regions have a distance bigger (i.e.

Abstract: A bipolar punch-through semiconductor device has a semiconductor substrate, which includes at least a two-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact. One of the layers in the two-layer structure is a base layer of the first conductivity type. A buffer layer of the first conductivity type is arranged on the base layer. A first layer includes alternating first regions of the first conductivity type and second regions of the second conductivity type. The first layer is arranged between the buffer layer and the second electrical contact. The second regions are activated regions with a depth of at maximum 2 ?m and a doping profile, which drops from 90% to 10% of the maximum doping concentration within at most 1 ?m.

Abstract: A reverse-conducting semiconductor device includes a freewheeling diode and an insulated gate bipolar transistor (IGBT) on a common wafer. Part of the wafer forms a base layer with a base layer thickness. The IGBT includes a collector side and an emitter side arranged on opposite sides of the wafer. A first layer of a first conductivity type and a second layer of a second conductivity type are alternately arranged on the collector side. The first layer includes at least one first region with a first region width and at least one first pilot region with a first pilot region width. The second layer includes at least one second region with a second region width and at least one second pilot region with a second pilot region width. Each second region width is equal to or larger than the base layer thickness, whereas each first region width is smaller than the base layer thickness. Each second pilot region width is larger than each first pilot region width.

Abstract: A power semiconductor device, such as a power diode, and a method for producing such a device, are disclosed. The device includes a first layer of a first conductivity type, a second layer of a second conductivity type arranged in a central region on a first main side of the first layer, a third electrically conductive layer arranged on the second layer, and a fourth electrically conductive layer arranged on the first layer at a second main side opposite to the first main side. A junction termination region surrounds the second layer with self-contained sub-regions of the second conductivity type. A spacer region is arranged between the second layer and the junction termination region and includes a self-contained spacer sub-region of the second conductivity type which is electrically disconnected from the second layer.

Abstract: A fast recovery diode includes a base layer of a first conductivity type. The base layer has a cathode side and an anode side opposite the cathode side. An anode buffer layer of a second conductivity type having a first depth and a first maximum doping concentration is arranged on the anode side. An anode contact layer of the second conductivity type having a second depth, which is lower than the first depth, and a second maximum doping concentration, which is higher than the first maximum doping concentration, is also arranged on the anode side. A space charge region of the anode junction at a breakdown voltage is located in a third depth between the first and second depths. A defect layer with a defect peak is arranged between the second and third depths.

Abstract: A diode for fast switching applications includes a base layer of a first conductivity type with a first main side and a second main side opposite the first main side, an anode layer of a second conductivity type, which is arranged on the second main side, a plurality of first zones of the first conductivity type with a higher doping concentration than the base layer, and a plurality of second zones of the second conductivity type. The first and second zones are arranged alternately on the first main side. A cathode electrode is arranged on top of the first and second zones on the side of the zones which lies opposite the base layer, and a anode electrode is arranged on top of the anode layer on the side of the anode layer which lies opposite the base layer. The base layer includes a first sublayer, which is formed by the second main sided part of the base layer, and a second sublayer, which is formed by the first main sided part of the base layer.

Abstract: A reverse-conducting semiconductor device is disclosed with an electrically active region, which includes a freewheeling diode and an insulated gate bipolar transistor on a common wafer. Part of the wafer forms a base layer with a base layer thickness. A first layer of a first conductivity type with at least one first region and a second layer of a second conductivity type with at least one second and third region are alternately arranged on the collector side. Each region has a region area with a region width surrounded by a region border. The RC-IGBT can be configured such that the following exemplary geometrical rules are fulfilled: each third region area is an area, in which any two first regions have a distance bigger (i.e.

Abstract: A reverse-conducting insulated gate bipolar transistor includes a wafer of first conductivity type with a second layer of a second conductivity type and a third layer of the first conductivity type. A fifth electrically insulating layer partially covers these layers. An electrically conductive fourth layer is electrically insulated from the wafer by the fifth layer. The third through the fifth layers form a first opening above the second layer. A sixth layer of the second conductivity type and a seventh layer of the first conductivity type are arranged alternately in a plane on a second side of the wafer. A ninth layer is formed by implantation of ions through the first opening using the fourth and fifth layers as a first mask.

Abstract: A controlled-punch-through semiconductor device with a four-layer structure is disclosed which includes layers of different conductivity types, a collector on a collector side, and an emitter on an emitter side which lies opposite the collector side. The semiconductor device can be produced by a method performed in the following order: producing layers on the emitter side of wafer of a first conductivity type; thinning the wafer on a second side; applying particles of the first conductivity type to the wafer on the collector side for forming a first buffer layer having a first peak doping concentration in a first depth, which is higher than doping of the wafer; applying particles of a second conductivity type to the wafer on the second side for forming a collector layer on the collector side; and forming a collector metallization on the second side.

Abstract: A method of manufacturing a power semiconductor device is provided. A first oxide layer is produced on a first main side of a substrate of a first conductivity type. A structured gate electrode layer with at least one opening is then formed on the first main side on top of the first oxide layer. A first dopant of the first conductivity type is implanted into the substrate on the first main side using the structured gate electrode layer as a mask, and the first dopant is diffused into the substrate. A second dopant of a second conductivity type is then implanted into the substrate on the first main side, and the second dopant is diffused into the substrate. After diffusing the first dopant into the substrate and before implanting the second dopant into the substrate, the first oxide layer is partially removed. The structured gate electrode layer can be used as a mask for implanting the second dopant.