Abstract: A pseudo-triple-port memory is provided that includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port including a first word line coupled to a first bit line through a first access transistor, a second read port including a second word line coupled to a second bit line through a second access transistor, and a write port including both the word lines, both the bit lines, and the pair of access transistors.

Abstract: A charge-transfer transistor couples between a bit line and a sense node for a sense amplifier. During a read operation, a charge-transfer driver drives a gate voltage of the charge-transfer transistor to control whether the charge-transfer transistor conducts during a charge-transfer period. To assist the charge-transfer by the charge-transfer transistor, a first and second cross-coupled transistor are coupled between the bit line and a complement bit line.

Abstract: A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

Abstract: Certain aspects of the present disclosure are directed to a memory system. The memory system generally includes a word line (WL) driver circuit comprising a transistor coupled between a WL of a memory and a reference potential node. The memory system also includes a clamping circuit having logic configured to generate a control signal to drive a gate of the transistor such that the control signal is floating when the first head switch is open, and a first head switch coupled between a voltage rail and a supply input of the logic.

Abstract: A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A burst mode address comparator compares a current row address to a previous row address to determine whether a read operation is a normal read operation or a burst mode read operation.

Abstract: A method and apparatus for writing data to a memory device are provided that do not change the precharge states for a bit line pair in a current write cycle if the current data bit is unchanged from the preceding write cycle.

Abstract: A method and apparatus for writing data to a memory device are provided that do not change the precharge states for a bit line pair in a current write cycle if the current data bit is unchanged from the preceding write cycle.

Abstract: A method and apparatus for writing data to a memory device are provided that do not change the precharge states for a bit line pair in a current write cycle if the current data bit is unchanged from the preceding write cycle.

Abstract: A bit line and word line tracking circuit is provided that accounts for the power-supply-voltage-dependent delays in a memory having a logic power domain powered by a logic power supply voltage and a memory power domain powered by a memory power supply voltage.

Abstract: A memory and a method for operating the memory are provided. The memory includes a bitline and at least one memory cell coupled to the bitline. A bitline precharge circuit is configured to precharge the bitline for a memory access and to deactivate to float the bitline in a standby state. A reference circuit is configured to charge a load circuit to a voltage in the standby state. In one example, the load circuit includes a dummy bitline having a substantially same or greater electrical characteristic of the bitline. The reference circuit includes a dummy bitline precharge circuit configured to charge the dummy bitline to the voltage in the standby state.

Abstract: A data latch includes a first stage configured to receive an input in a first voltage domain, and a second stage. The second stage includes a level shifter configured to shift the input from the first voltage domain to a second voltage domain, and an output circuit having a pull down circuit and pull up circuit arranged to generate an output in the second voltage domain, wherein the pull down circuit is responsive to the input in the first voltage domain and the pull up circuit is responsive to the input in the second voltage domain.