Patents by Inventor Arun Rao

Arun Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11968674
    Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive, from a base station, a control message indicating a resource configuration for uplink and downlink transmissions. The UE may determine an uplink buffer threshold for a modem buffer of the UE based on the resource configuration. The UE may transmit, to the base station, a feedback request message requesting that the base station provide feedback for at least one previously transmitted uplink packet based on a comparison of an amount of previously transmitted uplink data and scheduled uplink data stored in the modem buffer relative to the uplink buffer threshold. The UE may receive, based on transmitting the feedback request message, a feedback response message corresponding to a first previously transmitted uplink packet of the at least one previously transmitted uplink packet.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: April 23, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Arnaud Meylan, Sitaramanjaneyulu Kanamarlapudi, Vishal Dalmiya, Kuo-Chun Lee, Shailesh Maheshwari, Vaishakh Rao, Arun Prasanth Balasubramanian, Subashini Krishnamurthy, Leena Zacharias, Sivashankar Sekar, Saket Bathwal, Liangchi Hsu, Raghuveer Ramakrishna Srinivas Tarimala
  • Patent number: 11953184
    Abstract: A light assembly includes a mounting bracket, a light coupled to the mounting bracket, a guide sensor coupled to the mounting bracket, a movement mechanism coupled to the mounting bracket, and a controller operably coupled to the light assembly. The controller is configured to receive data from the guide sensor and command actuation of the movement mechanism in response to the data received from the guide sensor.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: April 9, 2024
    Assignee: GOODRICH LIGHTING SYSTEMS, INC.
    Inventors: Sambasiva Rao Kodati, Arun Kumar Asoka Kumar, Praveen Kumar Busaji
  • Publication number: 20240113986
    Abstract: Various embodiments include an automobile network device that includes a descriptor sorting engine (DSE). The DSE may include a direct memory access (DMA) controller, a memory organized by channel clusters that each include a plurality of first-in first-out (FIFO) memories, a timer, and a time stamp (TS) sorting logic component. The DMA controller may be configured to pull timestamp-pointer pairs from packet descriptors stored in an unsorted descriptor ring memory, store the timestamp-pointer pairs in the FIFO memories, trigger the TS sorting logic component to reorder the timestamp-pointer pairs in the FIFO memories so that they are sorted in ascending order, use the sorted timestamp-pointer pairs in the FIFO memories to read the packet descriptors stored in an unsorted descriptor ring memory, and store the packet descriptors in a sorted descriptor ring memory.
    Type: Application
    Filed: October 3, 2022
    Publication date: April 4, 2024
    Inventors: Narasimha Rao KORAMUTLA, Arun GOTHEKAR, Susheel Kumar Yadav YADAGIRI, Akshat GUPTA, Srinivas MARAKALA, Naveen Kumar NARALA, Radvajesh MUNIBYRAIAH
  • Publication number: 20240109514
    Abstract: Systems and methods are provided for recording video of a driver in a vehicle and a surrounding visual field of the driver. The system includes a detachable body coupled to a windshield of a vehicle. The system further includes three or more cameras coupled to the detachable body. The three or more cameras are configured to capture surrounding views from the detachable body. One of the three or more cameras faces a driver seat of the vehicle in response to the detachable body being coupled to the windshield of the vehicle. The video may be processed by the system, the cloud, or a combination of them.
    Type: Application
    Filed: December 13, 2023
    Publication date: April 4, 2024
    Applicant: NETRADYNE, INC.
    Inventors: David Jonathan JULIAN, Sandeep PANDYA, Adam David KAHN, Michael CAMPOS, Avneesh AGRAWAL, Venkata Sreekanta Reddy ANNAPUREDDY, Lance Steven HETHERINGTON, Tejeswara Rao GUDENA, Suresh Babu YANAMALA, Arun VALIAPARAMBIL
  • Publication number: 20240103054
    Abstract: Systems and methods for coordinating data sampling among devices include a set of electronic devices that may periodically sample energy data from a smart meter according to sample timing information. The sample timing information may specify a set of times to sample energy data for each electronic device. The set of electronic devices may take turns in sampling energy data from the smart meter so that individual electronic devices may reduce power consumption by sampling less frequently. A server may determine the sample times for the electronic devices and may instruct the electronic devices to sample energy data. Additionally, each individual electronic device may leave and/or join wireless communication networks less frequently than if each individual electronic device performed every sample. Accordingly, the coordinated sampling may decrease the radio resource usage and/or bandwidth usage of any individual electronic device.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 28, 2024
    Inventors: Arun Vijayakumari Mahasenan, Venkateswara Rao Manepalli
  • Publication number: 20240107544
    Abstract: The present disclosure relates to techniques for localizing devices connected to wireless networks, such as wireless mesh networks. In particular, a device connected to a wireless mesh network may maintain and share information, such as location data and identifiers, regarding the device and other devices connected to the device. The device itself or a computing system to which the device connects may determine locations for the devices in the wireless mesh network and generate a device map that indicates the locations of the devices.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Arun Vijayakumari Mahasenan, Venkateswara Rao Manepalli, Langford M Wasada
  • Publication number: 20240079132
    Abstract: In an embodiment, an electronic device includes a display screen, a memory circuit, and computing circuitry, which is coupled to the display screen and to the memory circuit, and which is configured to cause the display screen to display icons that are each related to respective data regarding a patient at a medical facility, to retrieve, from the memory, the respective data in response to a user of the electronic device selecting, via the display screen, a corresponding one of the displayed icons, and to cause the display screen to display the retrieved respective data.
    Type: Application
    Filed: July 11, 2023
    Publication date: March 7, 2024
    Applicant: BFC MED LLC
    Inventors: Arun Rao, Lacey Rao
  • Patent number: 11799466
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transmit signal in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer including coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: October 24, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sarvesh Bang, Arun Rao, Joseph Pham
  • Patent number: 11728031
    Abstract: In an embodiment, an electronic device includes a display screen, a memory circuit, and computing circuitry, which is coupled to the display screen and to the memory circuit, and which is configured to cause the display screen to display icons that are each related to respective data regarding a patient at a medical facility, to retrieve, from the memory, the respective data in response to a user of the electronic device selecting, via the display screen, a corresponding one of the displayed icons, and to cause the display screen to display the retrieved respective data.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: August 15, 2023
    Assignee: BFC MED LLC
    Inventors: Arun Rao, Lacey Rao
  • Patent number: 11528026
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: December 13, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mayank Garg, Shu-Ing Ju, Arun Rao, Wei Zhang
  • Patent number: 11436504
    Abstract: Indications of static objects (e.g., lane segments, signs etc.) and dynamic objects (e.g., moving vehicles, pedestrians and the like) in the operation environment of a vehicle are obtained. A graph comprising a plurality of nodes and edges is generated. Individual ones of the nodes represent respective static and dynamic objects, and an edge between a first pair of nodes represents a relationship between the objects represented by the pair. The graph includes an indication of an uncertainty metric associated with the relationship. To generate the graph, a geometric analysis is performed, as a result of which an edge between a different pair of nodes is excluded from the graph. Using the graph, one or more operations of a task pertaining to vehicle movements is performed.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: September 6, 2022
    Assignee: Apple Inc.
    Inventors: Dimitar Hristov Lukarski, Luke Burke Johnson, Arun Rao, Siddharth Swaminathan
  • Publication number: 20210250021
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transmit signal in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer including coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.
    Type: Application
    Filed: April 29, 2021
    Publication date: August 12, 2021
    Inventors: Sarvesh Bang, Arun Rao, Joseph Pham
  • Patent number: 11075620
    Abstract: Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: July 27, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shuing Ju, Wenxiao Tan, Arun Rao
  • Patent number: 11025242
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transmit signal in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer including coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: June 1, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Sarvesh Bang, Arun Rao, Joseph Pham
  • Publication number: 20210044294
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.
    Type: Application
    Filed: October 28, 2020
    Publication date: February 11, 2021
    Inventors: Mayank Garg, Shu-Ing Ju, Arun Rao, Wei Zhang
  • Publication number: 20210028775
    Abstract: Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.
    Type: Application
    Filed: October 15, 2020
    Publication date: January 28, 2021
    Inventors: Shuing Ju, Wenxiao Tan, Arun Rao
  • Patent number: 10855263
    Abstract: Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: December 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shuing Ju, Wenxiao Tan, Arun Rao
  • Patent number: 10855275
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: December 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mayank Garg, Shu-Ing Ju, Arun Rao, Wei Zhang
  • Publication number: 20200350905
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transmit signal in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer including coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Sarvesh Bang, Arun Rao, Joseph Pham
  • Patent number: 10763844
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transmit signals in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: September 1, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Sarvesh Bang, Arun Rao, Joseph Pham