Patents by Inventor Arun Rao
Arun Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12367977Abstract: In an embodiment, an electronic device includes a display screen, a memory circuit, and computing circuitry, which is coupled to the display screen and to the memory circuit, and which is configured to cause the display screen to display icons that are each related to respective data regarding a patient at a medical facility, to retrieve, from the memory, the respective data in response to a user of the electronic device selecting, via the display screen, a corresponding one of the displayed icons, and to cause the display screen to display the retrieved respective data.Type: GrantFiled: May 30, 2024Date of Patent: July 22, 2025Assignee: BFC MED LLCInventors: Arun Rao, Lacey Rao
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Publication number: 20240404695Abstract: In an embodiment, an electronic device includes a display screen, a memory circuit, and computing circuitry, which is coupled to the display screen and to the memory circuit, and which is configured to cause the display screen to display icons that are each related to respective data regarding a patient at a medical facility, to retrieve, from the memory, the respective data in response to a user of the electronic device selecting, via the display screen, a corresponding one of the displayed icons, and to cause the display screen to display the retrieved respective data.Type: ApplicationFiled: May 30, 2024Publication date: December 5, 2024Applicant: BFC MED LLCInventors: ARUN RAO, LACEY RAO
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Publication number: 20240372423Abstract: A rotor assembly includes a rotor core that defines a plurality of cavities and includes a plurality of laminations having annular bodies and stackably arranged to form the rotor core. The plurality of laminations includes a plurality of notch laminations and at least one tab lamination. Each notch lamination defines a plurality of first apertures. Each first aperture has a notch at a portion of the first aperture. The tab lamination defines a plurality of second apertures and includes flexible tabs extending toward the second apertures. The plurality of first apertures and the plurality of second apertures define at least a portion of the plurality of the cavities. A set of notch laminations are stacked with the tab lamination, where the notches of the set of notch laminations align with the flexible tabs of the tab lamination.Type: ApplicationFiled: May 3, 2023Publication date: November 7, 2024Inventors: Singar RATHNAM, Arun Rao MADHARAPU, Matthew SCHMITT, Jacob KRIZAN
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Patent number: 12080424Abstract: In an embodiment, an electronic device includes a display screen, a memory circuit, and computing circuitry, which is coupled to the display screen and to the memory circuit, and which is configured to cause the display screen to display icons that are each related to respective data regarding a patient at a medical facility, to retrieve, from the memory, the respective data in response to a user of the electronic device selecting, via the display screen, a corresponding one of the displayed icons, and to cause the display screen to display the retrieved respective data.Type: GrantFiled: July 11, 2023Date of Patent: September 3, 2024Inventors: Arun Rao, Lacey Rao
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Publication number: 20240079132Abstract: In an embodiment, an electronic device includes a display screen, a memory circuit, and computing circuitry, which is coupled to the display screen and to the memory circuit, and which is configured to cause the display screen to display icons that are each related to respective data regarding a patient at a medical facility, to retrieve, from the memory, the respective data in response to a user of the electronic device selecting, via the display screen, a corresponding one of the displayed icons, and to cause the display screen to display the retrieved respective data.Type: ApplicationFiled: July 11, 2023Publication date: March 7, 2024Applicant: BFC MED LLCInventors: Arun Rao, Lacey Rao
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Patent number: 11799466Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transmit signal in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer including coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.Type: GrantFiled: April 29, 2021Date of Patent: October 24, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sarvesh Bang, Arun Rao, Joseph Pham
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Patent number: 11728031Abstract: In an embodiment, an electronic device includes a display screen, a memory circuit, and computing circuitry, which is coupled to the display screen and to the memory circuit, and which is configured to cause the display screen to display icons that are each related to respective data regarding a patient at a medical facility, to retrieve, from the memory, the respective data in response to a user of the electronic device selecting, via the display screen, a corresponding one of the displayed icons, and to cause the display screen to display the retrieved respective data.Type: GrantFiled: October 14, 2019Date of Patent: August 15, 2023Assignee: BFC MED LLCInventors: Arun Rao, Lacey Rao
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Patent number: 11528026Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.Type: GrantFiled: October 28, 2020Date of Patent: December 13, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mayank Garg, Shu-Ing Ju, Arun Rao, Wei Zhang
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Patent number: 11436504Abstract: Indications of static objects (e.g., lane segments, signs etc.) and dynamic objects (e.g., moving vehicles, pedestrians and the like) in the operation environment of a vehicle are obtained. A graph comprising a plurality of nodes and edges is generated. Individual ones of the nodes represent respective static and dynamic objects, and an edge between a first pair of nodes represents a relationship between the objects represented by the pair. The graph includes an indication of an uncertainty metric associated with the relationship. To generate the graph, a geometric analysis is performed, as a result of which an edge between a different pair of nodes is excluded from the graph. Using the graph, one or more operations of a task pertaining to vehicle movements is performed.Type: GrantFiled: June 5, 2019Date of Patent: September 6, 2022Assignee: Apple Inc.Inventors: Dimitar Hristov Lukarski, Luke Burke Johnson, Arun Rao, Siddharth Swaminathan
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Publication number: 20210250021Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transmit signal in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer including coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.Type: ApplicationFiled: April 29, 2021Publication date: August 12, 2021Inventors: Sarvesh Bang, Arun Rao, Joseph Pham
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Patent number: 11075620Abstract: Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.Type: GrantFiled: October 15, 2020Date of Patent: July 27, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shuing Ju, Wenxiao Tan, Arun Rao
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Patent number: 11025242Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transmit signal in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer including coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.Type: GrantFiled: July 20, 2020Date of Patent: June 1, 2021Assignee: Texas Instruments IncorporatedInventors: Sarvesh Bang, Arun Rao, Joseph Pham
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Publication number: 20210044294Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.Type: ApplicationFiled: October 28, 2020Publication date: February 11, 2021Inventors: Mayank Garg, Shu-Ing Ju, Arun Rao, Wei Zhang
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Publication number: 20210028775Abstract: Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.Type: ApplicationFiled: October 15, 2020Publication date: January 28, 2021Inventors: Shuing Ju, Wenxiao Tan, Arun Rao
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Patent number: 10855275Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.Type: GrantFiled: April 30, 2019Date of Patent: December 1, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mayank Garg, Shu-Ing Ju, Arun Rao, Wei Zhang
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Patent number: 10855263Abstract: Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.Type: GrantFiled: May 31, 2019Date of Patent: December 1, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shuing Ju, Wenxiao Tan, Arun Rao
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Publication number: 20200350905Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transmit signal in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer including coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.Type: ApplicationFiled: July 20, 2020Publication date: November 5, 2020Inventors: Sarvesh Bang, Arun Rao, Joseph Pham
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Patent number: 10763844Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transmit signals in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.Type: GrantFiled: August 27, 2019Date of Patent: September 1, 2020Assignee: Texas Instruments IncorporatedInventors: Sarvesh Bang, Arun Rao, Joseph Pham
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Publication number: 20200118680Abstract: In an embodiment, an electronic device includes a display screen, a memory circuit, and computing circuitry, which is coupled to the display screen and to the memory circuit, and which is configured to cause the display screen to display icons that are each related to respective data regarding a patient at a medical facility, to retrieve, from the memory, the respective data in response to a user of the electronic device selecting, via the display screen, a corresponding one of the displayed icons, and to cause the display screen to display the retrieved respective data.Type: ApplicationFiled: October 14, 2019Publication date: April 16, 2020Inventors: Arun Rao, Lacey Rao
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Publication number: 20200076416Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transmit signals in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.Type: ApplicationFiled: August 27, 2019Publication date: March 5, 2020Inventors: Sarvesh Bang, Arun Rao, Joseph Pham