Abstract: In an embodiment, an electronic device includes a display screen, a memory circuit, and computing circuitry, which is coupled to the display screen and to the memory circuit, and which is configured to cause the display screen to display icons that are each related to respective data regarding a patient at a medical facility, to retrieve, from the memory, the respective data in response to a user of the electronic device selecting, via the display screen, a corresponding one of the displayed icons, and to cause the display screen to display the retrieved respective data.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transmit signals in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.

Abstract: Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.

Abstract: A file format that includes a constant section and a varying section. The constant section provides a referencing scheme that references the various components that comprise the scene, as well as a listing of attributes of the scene that are modifiable. Within the same file format, the varying section provides an overriding mechanism to modify the attributes that are available to be modified. Accordingly, the disclosed file format can access cached animated geometry directly and/or aggregate other files via the aforementioned referencing and sparse override semantics. This allows the same set of inspection, manipulation, and rendering tools to be used throughout the rendering pipeline, from asset creation to final rendering.

Abstract: A file format that includes a constant section and a varying section. The constant section provides a referencing scheme that references the various components that comprise the scene, as well as a listing of attributes of the scene that are modifiable. Within the same file format, the varying section provides an overriding mechanism to modify the attributes that are available to be modified. Accordingly, the disclosed file format can access cached animated geometry directly and/or aggregate other files via the aforementioned referencing and sparse override semantics. This allows the same set of inspection, manipulation, and rendering tools to be used throughout the rendering pipeline, from asset creation to final rendering.

Abstract: Presented herein is a method and system for reducing memory requirements in audio signal processing by de-interleaving audio information with at least two static buffers and a dynamic buffer. The method may include writing interleaved audio information to a first static memory device. The method may also include de-interleaving the audio information and writing de-interleaved audio information to a second static memory device. The method may also include writing de-interleaved audio information to a dynamic memory device from the second static memory device and overwriting interleaved audio information with new interleaved audio information in the first static memory device. The method may also include overwriting interleaved audio information in the first static memory device with de-interleaved audio information from the dynamic memory device and decoding the audio information.

Abstract: Systems and methods for categorizing and mapping telecommunication services are provided. In this regard, a representative system in a communication, media, and entertainment (CME) environment, among others, includes at least one service provider that is a part of the CME environment. The service provider includes a computing device having a processing device that facilitates execution of programs stored in the computing device, and memory that is electrically coupled to the processing device. The memory is configured to store the programs that include a taxonomy manager, the taxonomy manager being configured to identify entities of a communication, media and entertainment environment (CME). The CME environment includes at least one service provider having multiple telecommunication platforms. The entities are associated with the multiple telecommunication platforms.

Abstract: A switch array circuit that enables voltage regulation by bucking a relatively larger input voltage as it declines over time with different fractional gains that are based on different gain phase arrangements for a plurality of capacitors. A common rest phase is provided during the switching between the different gain phases. The rest phase inherently enables power to be conserved during gain transitions. Increasingly larger fractional gain phases (less buck) is provided as the input voltage declines over time, e.g., from ? to ? to ½ to ? to unity, and the like. Also, the common rest phase for the plurality of capacitors is arranged to minimize fluctuation of the output voltage during switching between phases to generate a selected gain from the gain phase. Additionally, the common rest phase conserves/stores energy during switching transitions between multiple gain phases. The stored energy in the common rest phase can be subsequently reused in the gain phases.

Abstract: Presented herein are systems and methods for computing the product of a constant and a mixed number power of two. A circuit comprises a first register, a second register, a memory, a third register, and a multiplier circuit. The first register stores the constant. The second register stores the integer portion and the fraction portion. The memory stores a plurality of values, each of said plurality of values corresponding to a particular one of a corresponding plurality of fractions, wherein each one of said plurality of values is two to the exponential fraction corresponding to the one of said plurality of values. The third register stores a particular one of the plurality of values, said particular one of the plurality of values corresponding to the fraction portion. The multiplier circuit multiplies the contents of the third register by the contents of the first register, thereby resulting in a product.

Abstract: A system and method of modelling a communications network using a computer system is disclosed, the method including generating a network representation using computer-readable code that represents structured information; parsing the network representation; generating a network model using the parsed network representation, the network model including a plurality of network objects and relationships between the plurality of network objects; and storing the network model in memory. Any type of network may be modeled. The computer-readable code may be any suitable language or instructions for representing structured information such as, for example, extensible mark-up language (XML). A network inventory adapter receives the network representation from the network. The network inventory adapter is a software component that may be used to connect applications to the network.

Abstract: A multi-stage transistor circuit is provided in which the multiple transistor stages are coupled in parallel and switched individually in sequence by a series arrangement of buffers. Each buffer drives the gate of a corresponding stage of the multi-stage transistor circuit with a gating signal that is delayed by each buffer. Optionally, the voltage of the gating signal can be varied. Each transistor stage may comprise one or more transistors in parallel. A switched capacitor DC/DC converter incorporating the multi-stage transistor circuit is provided in which parasitic ringing at the output is substantially reduced or eliminated. Additionally, the multi-stage transistor circuit is well suited for implementing an adaptive non-overlapping gating signal generator for complementarily driving a series arrangement of multi-stage transistors.

Abstract: A system, method, and apparatus for reducing the video decoder processing requirements are presented herein. During a rewind operation, a reference picture for a group of pictures is decoded and stored into a reference frame buffer. By storing a reference picture for the group, the reference picture need not be decoded to display each picture in the group during the rewind operation.

Abstract: A system for efficiently converting computer graphics images to film images with accurate color management is described. The system involves the creation of a direct mapping of chromaticity and intensity data from the values used to generate images on a computer monitor to the values used to display the images on projected motion picture film.

Abstract: A system and method for slowing down an audio signal while maintaining the same pitch as the original audio signal. The slowing down being done by a decoder. The method involves replicating frames of the decoded signal at a rate corresponding to the desired slow playback speed, and windowing the replicated frames to smooth out any artifacts that may result from the replication. The desired slow playback speed can be a default value predefined in the system or a value programmable by a user of the system.

Abstract: A system and method for speeding up an audio signal while maintaining the same pitch as the original audio signal. The speeding up being done by a decoder. The method involves skipping frames of the decoded signal at a rate corresponding to the desired fast playback speed, and windowing the remaining frames to smooth out any artifacts that may result from skipping frames. The desired fast playback speed can be a default value predefined in the system or a value programmable by a user of the system.

Abstract: Presented herein are systems and methods for computing the product of a constant and a mixed number power of two. A circuit comprises a first register, a second register, a memory, a third register, and a multiplier circuit. The first register stores the constant. The second register stores the integer portion and the fraction portion. The memory stores a plurality of values, each of said plurality of values corresponding to a particular one of a corresponding plurality of fractions, wherein each one of said plurality of values is two to the exponential fraction corresponding to the one of said plurality of values. The third register stores a particular one of the plurality of values, said particular one of the plurality of values corresponding to the fraction portion. The multiplier circuit multiplies the contents of the third register by the contents of the first register, thereby resulting in a product.

Abstract: A system for efficiently converting computer graphics images to film images with accurate color management is described. The system involves the creation of a direct mapping of chromaticity and intensity data from the values used to generate images on a computer monitor to the values used to display the images on projected motion picture film.

Abstract: A system for efficiently converting computer graphics images to film images with accurate color management is described. The system involves the creation of a direct mapping of chromaticity and intensity data from the values used to generate images on a computer monitor to the values used to display the images on projected motion picture film.

Abstract: Presented herein is a method and system for reducing the total memory required by an audio decoding device by providing audio decoder buffer optimization, memory overwriting capability during audio decoding, and ordered processing of audio decoder program operations. Memory may be reduced by applying the buffer overlaying method to reduce the amount of memory to perform audio decoding to a minimum amount of memory. Audio decoding devices implementing the memory reducing method may be provided with a minimum amount of memory, reducing the cost of the audio decoding devices while efficiently decoding audio signals.