Abstract: One aspect of the present invention relates to a system and method for monitoring in-situ a chemical composition at or near a surface of a wafer during plasma etch to detect defects The method involves the steps of providing a semiconductor substrate comprising at least one top layer, wherein the semiconductor substrate comprises at least one chemical-containing contaminant; subjecting the semiconductor substrate to a plasma etch process, whereby at least a portion of the top layer is removed; during the plasma etch process, detecting for a presence of the chemical-containing contaminant using one of an Auger Electron Spectroscopy system or Energy Dispersive X-ray Analysis system; and if present, determining whether the presence of the chemical-containing contaminant exceeds a threshold limit.

Abstract: The invention provides a system and process for depositing films, wherein an acoustic microbalance is used for process monitoring and/or control. The acoustic microbalance is placed in a deposition chamber and may optionally be mounted on a semiconductor substrate, such as a silicon wafer, on which a film is being deposited. Data from the acoustic microbalance is employed to detect a process endpoint, determine an adjustment to process conditions for a subsequent batch, and/or provide feedback control over current process conditions. One aspect of the invention involves the application of a model or database to correct for differences between the extent of deposition on an acoustic microbalance cantilever and the extent of deposition on a substrate being processed. Another aspect of the invention takes a probabilistic approach to employing acoustic microbalance data.

Abstract: A semiconductor device which includes a precision high-K dielectric and formed on a semiconductor substrate and a method of forming the same. The semiconductor device includes at least one dielectric layer having a dielectric constant greater than SiO2. The at least one dielectric layer is deposited by atomic layer deposition (ALD). The ALD deposited layer has precise uniformity, thickness and abrupt atomic interfaces.

Abstract: The present invention, in one embodiment, relates to a process for fabricating a semiconductor device that is less susceptible to performance degradation caused by hydrogen contamination. The method includes the steps for removing unwanted hydrogen bonds by exposing the hydrogen bonds to ultraviolet radiation sufficient to break the bond and annealing in an atmosphere comprising at least one gas having at least one atom capable of forming bonds that replace the hydrogen bonds.

Abstract: A semiconductor device and method of making the same includes a first metallization level, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer and the first etch stop layer. The first etch stop layer is disposed over the first metallization level. Metal within the opening forms a second metal feature, and the metal can comprise copper or a copper alloy. Dopants are introduced into the metal and are activated by laser thermal annealing. A concentration of the dopants within the metal in a lower portion of the second metal feature proximate the first metal feature is greater than a concentration of dopants in a central portion of the second metal feature, and a concentration of the dopants within the metal in an upper portion of the second metal feature is greater than a concentration of dopants in the central portion of the second metal feature.

Abstract: A system for regulating gate oxide layer formation is provided. The system includes one or more light sources, each light source directing light to one or more gate oxide layers being deposited and/or formed on a wafer. Light reflected from the gate oxide layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the thickness and/or uniformity of the respective gate oxide layers on the wafer. The measuring system provides thickness and/or uniformity related data to a processor that determines the thickness and/or uniformity of the respective gate oxide layers on the wafer. The system also includes a plurality of gate oxide layer formers where each gate oxide former corresponds to a respective portion of the wafer and provides for gate oxide layer formation thereon. The processor selectively controls the gate oxide layer formers to regulate gate oxide layer formation on the respective gate oxide layer formations on the wafer.

Abstract: Reliable Cu interconnects are formed by filling an opening in a dielectric layer with Cu and then laser thermal annealing in NH3 to reduce copper oxide and to reflow the deposited Cu, thereby eliminating voids and reducing contact resistance. Embodiments include laser thermal annealing employing an NH3 flow rate of about 200 to about 2,000 sccn.

Abstract: A system for regulating nitrided gate oxide layer formation is provided. The system includes one or more light sources, each light source directing light to one or more nitrided gate oxide layers being deposited and/or formed on a wafer. Light reflected from the nitrided gate oxide layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the nitrogen concentration of the respective nitrided gate oxide layers on the wafer. The measuring system provides nitrogen concentration related data to a processor that determines the nitrogen concentration of the respective nitrided gate oxide layers on the wafer. The system also includes one or more nitrided gate oxide layer formers where a nitride gate oxide former corresponds to a respective portion of the wafer and provides for nitrided gate oxide layer formation thereon.

Abstract: A flash memory structure and its fabrication process, whereby stacks, of a first poly-crystalline silicon material or an amorphous silicon material (polysilicon), are processed for formation of a pre-interpoly dielectric treatment layer over the first polysilicon material. The pre-interpoly dielectric treatment layer being a solid material formed by a chemical reaction formed for purposes of improving the reliability of an interpoly dielectric member and results in changing the capacitor coupling ratio of the flash memory element and allows the use of new power supply and programming voltages. The pre-interpoly dielectric treatment layer is formed by exposing the polysilicon stacks to a selected one of at least three ambient reagent gases. The selected gaseous ambient and exposure of the polysilicon stacks being performed in a fabrication tool such as a batch furnace, a single wafer rapid thermal anneal tool, or a plasma chamber.

Abstract: A process to deposit a silicon dioxide layer on a silicon nitride layer for an ONO stack of a floating gate transistor. Silicon dioxide is deposited on a silicon nitride layer and annealed in a batch furnace or a single wafer rapid thermal anneal tool in a nitrogen oxide (NO) or nitrous oxide (N2O) ambient environment.

Abstract: A semiconductor device and a process for fabricating the device, including, in one embodiment, a silicon substrate; a first interfacial barrier layer on the silicon substrate, in which the first interfacial barrier layer may include aluminum oxide, silicon nitride, silicon oxynitride or a mixture thereof; and a layer of a high-K dielectric material. The device may further include a second interfacial barrier layer on the high-K dielectric material layer, and may further include a polysilicon or polysilicon-germanium gate electrode formed on the second interfacial barrier layer.

Abstract: A method of making and a semiconductor device formed on a semiconductor substrate having an active region. The semiconductor device includes a gate dielectric layer disposed on the semiconductor substrate. A floating gate is formed on the gate dielectric layer and defines a channel interposed between a source and a drain formed within the active region of the semiconductor substrate. A control gate is formed above the floating gate. Further, the semiconductor device includes an intergate dielectric layer interposed between the floating gate and the control gate. The intergate dielectric layer including a first, a second and a third layers. The first layer formed on the floating gate. The second layer formed on the first layer. The third layer formed on the second layer. Each of the first, second and third layers has a dielectric constant greater than SiO2 and an electrical equivalent thickness of less than about 50 angstroms (Å) of SiO2.

Abstract: A process for fabrication of a semiconductor device including a modified ONO structure, including forming the modified ONO structure by providing a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; depositing a layer comprising a high-K dielectric material on the first oxide layer; and forming a top oxide layer on the layer comprising a high-K dielectric material. The semiconductor device may be, e.g., a MIRRORBIT™ two-bit EEPROM device or a floating gate flash device including a modified ONO structure.

Abstract: A device and method for manufacturing thereof for a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.

Abstract: A method of manufacturing a semiconductor device etches a feature on a substrate in accordance with a photoresist mask. The photoresist mask is removed by plasma etching. Laser thermal annealing is performed to vaporize polymer residue created during the stripping of the photoresist mask, and to repair damage to the substrate.

Abstract: A method of manufacturing an integrated circuit includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer and a gate dielectric layer over the semiconductor substrate. Bitlines are implanted closely in the semiconductor substrate and annealed using a rapid thermal anneal. Wordlines and gates are formed and source/drain junctions are implanted in the semiconductor substrate. An interlayer dielectric layer is deposited and the integrated circuit completed.

Abstract: A semiconductor device and a method of fabricating the semiconductor device having a composite dielectric layer including steps of providing a semiconductor substrate; depositing on the semiconductor substrate alternating sub-layers of a first dielectric material and a second dielectric material to form a layered dielectric structure having at least two sub-layers of at least one of the first dielectric material and the second dielectric material, in which one of the first dielectric material and the second dielectric material is a high-K dielectric material and an other of the first dielectric material and the second dielectric material is a standard-K dielectric material comprising aluminum oxide; and annealing the layered dielectric structure at an elevated temperature to form a composite dielectric layer.

Abstract: An apparatus and a method of depositing a dielectric material film, including steps of initiating a process of depositing a dielectric material film under at least one controllable initial condition in an apparatus comprising a dielectric material deposition chamber and a spectroscopic ellipsometer; and measuring, by the spectroscopic ellipsometer, at least one ellipsometric parameter of the dielectric material film during the process of depositing the film.

Abstract: A process for fabrication of a semiconductor device including a modified ONO structure, comprising forming the modified ONO structure by providing a semiconductor substrate; forming a first dielectric material layer on the semiconductor substrate; depositing a silicon nitride layer on the first dielectric material layer; and forming a top dielectric material layer, wherein at least one of the bottom dielectric material layer and the top dielectric material layer comprise a mid-K or a high-K dielectric material. The semiconductor device may be, e.g., a SONOS two-bit EEPROM device or a floating gate flash device including the modified ONO structure.

Abstract: One aspect of the present invention relates to a method to facilitate formation of an oxide portion of an anti-reflective layer on a substrate. The method involves the steps of forming an oxidized portion of an anti-reflective coating over an anti-reflective layer disposed on the substrate; reflecting a beam of x-ray radiation at the oxidized portion; generating a measurement signal based on the reflected portion of the light beam; and determining a thickness of the oxidized portion based on the measurement signal while the oxidized portion is being formed at the substrate.