Abstract: A process for fabricating an ONO layer in a non-volatile memory device including the steps of forming a first silicon oxide layer, a silicon-rich silicon nitride layer and a second silicon oxide layer. The silicon-rich silicon nitride layer is formed by either a PECVD process, an LPCVD, or an RTCVD process. The silicon-rich silicon nitride layer effectively holds electrical charge making the ONO layer particularly useful as a floating gate electrode in a two-bit EEPROM device.

Abstract: A process for fabricating shallow pocket regions in a non-volatile semiconductor device includes providing a semiconductor substrate having a principal surface. A masking pattern is formed to overlie the principal surface that includes an opening therein. An angled, molecular ion implantation process is carried out to form first and second shallow pocket regions in the semiconductor substrate. The first and second pocket regions at least partially underlie the first and second sidewalls, respectively, of the opening in the patterned layer. Further processing steps are then carried out to form a bit-line region in a non-volatile semiconductor device.

Abstract: A process for fabricating a memory cell, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a masking layer overlying the ONO layer, patterning the masking layer into a resist mask, implanting the semiconductor substrate with a p-type dopant to create a p-type region, and laterally diffusing the p-type region. In one preferred embodiment, the lateral diffusing of the p-type region includes exposing the semiconductor substrate to a thermal cycle. Preferably, the thermal cycle is a rapid thermal anneal or a furnace anneal.

Abstract: A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a nitrogenated top oxide layer. The process includes the sequential formation of a silicon nitride layer and a top oxide layer using an in-situ LPCVD or RTCVD deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. After forming the top oxide layer, an annealing process is carried out to diffuse nitrogen into the top oxide layer. The formation of a nitrogenated top oxide layer provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.

Abstract: A flash memory structure and fabrication process whereby stacks of a first poly-crystalline or of an amorphous silicon material (polysilicon), having a bottom layer member of an interpoly dielectric stack, are processed for formation of a post-treatment layer over the bottom interpoly dielectric layer member. The post-treatment layer is essentially a solid material formed by a chemical reaction for purposes of improving the reliability of an interpoly dielectric stack and results in changes to the capacitor coupling ratio of the flash memory element and allows the use of new power supply and programming voltages. The post-treatment layer is formed by exposing the polysilicon stacks with the bottom interpoly dielectric layer member to a selected one of at least three ambient reagent gases. The selected ambient reagent gases and exposure of the semiconductor structure being performed in either a batch furnace, a single wafer rapid thermal anneal tool, or a plasma chamber.

Abstract: A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a top oxide layer using a high-temperature-oxide (HTO) deposition process in which the HTO process is carried out at a temperature of about 700 to about 800° C. by either an LPCVD or RTCVD deposition processor. The process further includes the sequential formation of a silicon nitride layer and a top oxide layer using an in-situ LPCVD or RTCVD deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. The formation of the top oxide layer using an HTO deposition process provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.

Abstract: A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes providing a semiconductor substrate and thermally growing a first silicon oxide layer overlying the semiconductor substrate. A thermal anneal is performed after growing the first silicon oxide layer in an ambient atmosphere of at least one of nitric oxide, nitrous oxide and ammonia. In this regard, nitrogen is incorporated into the first silicon oxide layer which leads to a better performance and a higher quality of the ONO structure. A silicon nitride layer is formed to overlie the first silicon oxide layer; and a second layer of silicon oxide is formed to overlie the silicon nitride layer to complete the ONO structure.

Abstract: A process for fabricating an ONO structure for a MONOS type Flash cell includes growing a first silicon oxide layer over a semiconductor substrate. Thereafter, a silicon nitride layer is formed to overlie the first silicon oxide layer, and a polycrystalline silicon layer is deposited to overlie the silicon nitride layer. By utilizing the polycrystalline silicon layer as the top layer of the ONO structure, a resist layer can be cleaned more aggressively than if the top layer of the ONO structure were an oxide layer. A second silicon oxide layer overlies the polycrystalline layer, of the ONO structure. Since the second silicon oxide layer is deposited on top of polycrystalline silicon after the resist material is cleaned, some resist material can remain on the polycrystalline layer without degrading the performance of the MONOS type cell.

Abstract: A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a first and second oxide layers using a high-temperature-oxide (HTO) deposition process in which the HTO process is carried out at a temperature of about 700 to about 800° C. The process further includes the sequential formation of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer using an RTCVD process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. The formation of the first and second oxide layers using an RTCVD process provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.

Abstract: A composition for making fired dielectric layers which is especially suitable for laser scribing consisting essentially of finely divided particles of dielectric glass, inorganic filler having a refractive index higher than the glass and cobalt oxide, all being dispersed in organic medium. The composition can be in the form of either thick film paste or green tape.

Abstract: An amorphous partially crystallizable alkaline earth zinc silicate glass containing ZrO.sub.2 and optionally small amounts of Al.sub.2 O.sub.3, HfO.sub.2, P.sub.2 O.sub.5 and TiO.sub.2.