Patents by Inventor Arvind M. Patel

Arvind M. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11481293
    Abstract: In general, embodiments of the invention relate to storing data and managing the stored data in linked nodes. More specifically, embodiments of the invention relate to nodes linked together in a daisy chain configuration such as, but not limited to, a single-chain configuration and a dual-chain configuration, which use data protection domain (DPD) information to determine where and/or how to store the data.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: October 25, 2022
    Assignee: Dell Products L.P.
    Inventors: Arvind Ramakrishnan Palamadai, Rizwan Ali, Dharmesh M. Patel, Ravikanth Chaganti
  • Patent number: 11422741
    Abstract: In general, embodiments of the invention relate to storing data and managing the stored data in linked nodes. More specifically, embodiments of the invention relate to nodes linked together in a daisy chain configuration such as, but not limited to, a single-chain configuration and a dual-chain configuration, which use data protection domain (DPD) information to determine where and/or how to store the data.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: August 23, 2022
    Assignee: Dell Products L.P.
    Inventors: Dharmesh M. Patel, Arvind Ramakrishnan Palamadai, Rizwan Ali, Ravikanth Chaganti
  • Patent number: 5559840
    Abstract: A digital timing recovery circuit for rapid acquisition and synchronization of sampling clock phase in a data playback signal processing channel. The filtered playback signal in a (1,7)ML coded playback channel is sampled at the rate of one sample per bit window and the digitized sample values are processed with a (1,7)ML decoding procedure to produce decoded bits. A digital timing recovery circuit of this invention uses the digitized sample values directly to control the sampling clock phase by computing a digital phase error signal (PES) that is a constant function of phase error independent of data pattern. The PES depends only on the adjacent samples before and after a peak signal value. These "side-samples" contain maximal timing information because they occur at the steepest slope of the read-back signal and are thus most sensitive to clock phase error.
    Type: Grant
    Filed: September 27, 1994
    Date of Patent: September 24, 1996
    Assignee: Inernational Business Machines Corporation
    Inventors: Constantin M. Melas, Arvind M. Patel, Robert A. Rutledge, Bum S. So
  • Patent number: 5491698
    Abstract: To improve data detection reliability in a coded maximum likelihood signal processing channel, two counters count the number of times actual values of linear functions of digital sample values corresponding to one and another preselected data patterns are within m units above and m units below, respectively, a preselected decision boundary used to determine whether detected data corresponding to a coded sequence of runlength limited code is a "1" or a "0". A difference count has a magnitude and sign denoting difference between counts in the two counters. After N occurrences of each preselected data pattern irrespective of how far from the boundary, the boundary is adjusted upwardly or downwardly, provided the difference count at least equals +S or at most -S, respectively.
    Type: Grant
    Filed: December 16, 1993
    Date of Patent: February 13, 1996
    Assignee: International Business Machines Corporation
    Inventors: Arvind M. Patel, Robert A. Rutledge, Bum S. So
  • Patent number: 5430745
    Abstract: Decoder for processing digital sample values corresponding to an incoming read signal representative of coded binary data. Functional expressions of digital sample values are precomputed for a preselected number of sample values ahead of a current sample value. To provide binary decision outputs, preselected functional expressions are compared against binary representations of corresponding thresholds that are conditioned by the sign of a selected functional expression comprising at least one preselected digital sample value. These outputs, the sign of the selected functional expression, the current value and previous value of decoded data, and the current value of detected phase, are all used to determine the next value of decoded data and next value of detected phase. These next values become the current values of decoded data and detected phase for the next clock cycle.
    Type: Grant
    Filed: February 17, 1994
    Date of Patent: July 4, 1995
    Assignee: International Business Machines Corporation
    Inventors: Arvind M. Patel, Robert A. Rutledge, Bum S. So
  • Patent number: 5353170
    Abstract: A direct access storage device (DASD) system uses a read/write head having a wide transducer write element and a narrow magneto-resistive read element. In order to avoid mistakenly reading a incompletely erased old data field, the system uses a verification procedure. Data are read at two positions along the data track which are separated by a radial distance D. This distance D is selected to be greater than the width of any incompletely erased data record. If the data read at the two read positions are equal, then the data are deemed to be correct and are sent to a host system.
    Type: Grant
    Filed: May 19, 1993
    Date of Patent: October 4, 1994
    Assignee: International Business Machines Corporation
    Inventors: Kwok W. Fung, Robert L. Kwok, Arvind M. Patel, Robert A. Rutledge
  • Patent number: 5291500
    Abstract: A signal processing channel and method are described for processing digital sample values corresponding to an incoming analog signal representative of coded binary data. An eight-sample look-ahead algorithm is used to precompute the values of functional expressions for a baseline check and for a peak-position check. These precomputed values are compared against appropriate thresholds to provide respective binary decision outputs which, with state values corresponding to the current state, are used to determine state values for the next state, which become the current state values for the next iteration of the clock cycle. During each of a series of successive clock cycles, one successive bit of coded binary data corresponding to said current sample value is decoded, and at the next clock cycle, the computed next state becomes the new current state. Sensitivity to missing or extra-bit errors is minimized and full advantage of a (1,7) run-length-limited code constraint is achieved.
    Type: Grant
    Filed: May 22, 1990
    Date of Patent: March 1, 1994
    Assignee: International Business Machines Corporation
    Inventors: Arvind M. Patel, Robert A. Rutledge
  • Patent number: 5282216
    Abstract: A method for processing, in a signal processing channel, digital values corresponding to a digitized incoming analog signal representative of coded binary data. A state-dependent sequence detection algorithm includes two groups of appropriate functional expressions of digital sample values, which expressions are identical but offset one sample position from each other. During each iterating step with successive pairs of clock cycles, the value of each expression in the two groups of expressions is precomputed from a preselected number of sample values ahead of a then current sample value; preselected ones of these expression values are compared against an appropriate threshold, which is the same for corresponding expressions of each group, to provide respective binary decision outputs corresponding to each of the two groups; and the current state value then advances to two next successive state values.
    Type: Grant
    Filed: July 27, 1992
    Date of Patent: January 25, 1994
    Assignee: International Business Machines Corporation
    Inventors: Arvind M. Patel, Robert A. Rutledge, Bum S. So
  • Patent number: 5266850
    Abstract: Method and circuitry for phase synchronizing an analog input signal with a clock signal by sensing clock delay error, adjusting in increments clock delay trim of a delay element that initially has an arbitrary delay setting, and stopping adjustment after differential delay between the signals has been eliminated.
    Type: Grant
    Filed: June 30, 1992
    Date of Patent: November 30, 1993
    Assignee: International Business Machines Corporation
    Inventors: Hoan A. Au, Arvind M. Patel, Robert A. Rutledge, Bum S. So, Albert S. Su
  • Patent number: 4945538
    Abstract: A method and apparatus for processing, in a signal processing channel, digital values corresponding to a digitized incoming analog signal representative of coded binary data. Using a state-dependent sequence detection algorithm appropriate functional expressions of digital sample values are precomputed at each cycle of the digitizing clock for a preselected number of bits ahead of the current bit. Preselected ones of these expressions are compared against corresponding thresholds to provide respective binary decision outputs that, with state values corresponding to the current state, determine state values for the next state and decode one bit of coded binary data at each clock cycle. Programmed values generated for the thresholds may be adaptively modified according to changes in sample values in the incoming analog signal relative to corresponding expected sample values. Different thresholds are used for positive and negative phases of the analog signal shape to accommodate signal shape asymmetry.
    Type: Grant
    Filed: November 14, 1988
    Date of Patent: July 31, 1990
    Assignee: International Business Machines Corporation
    Inventor: Arvind M. Patel
  • Patent number: 4916701
    Abstract: A method is disclosed for correcting multibyte errors in a magnetic medium on which data is recorded in variable length blocks that comprise subblocks of data bytes and corresponding check bytes and include error correction code (ECC) for which ECC syndromes are generated during reading. A sequence of N sequential parity check bytes is written at the end of each block. After ECC syndromes are generated during reading, parity syndromes are generated by comparing parity check bytes computed from data bytes and check bytes as read with the parity check bytes as written. When a long-burst error occurs, a pointer points to the first of the N consecutive bytes in a block that could have been influenced by the error burst. After correcting correctable errors in all subblocks not affected by the N bytes identified by the pointer, and adjusting the parity syndromes for errors thus corrected, the adjusted parity syndromes are used to correct the errors in the N bytes indicated by the pointer.
    Type: Grant
    Filed: September 21, 1988
    Date of Patent: April 10, 1990
    Assignee: International Business Machines Corporation
    Inventors: John S. Eggenberger, Paul Hodges, Arvind M. Patel
  • Patent number: 4849975
    Abstract: A method and apparatus is disclosed for correcting up to two byte errors in encoded uncorrected data in records of a predetermined length. As illustrated, the records are subblocks of a block in a multi-level error correction code format. The data is read from a storage device and corrected by decoding and processing four syndromes of error (S.sub.1, S.sub.2, S.sub.3, S.sub.0) that are generated by means disclosed in the prior art. These syndromes are decoded in response to uncorrected errors in any one record by computing vectors (P, Q, and R), which are functions of the four syndromes. Binary numbers (u and v) are then determined from these vectors by table look-up to enable calculation of one value (d) from the sum of said binary numbers for determining error locations. Another value (t), mathematically related to said one value, is then determined by table look-up and the error location values (y and z) are determined by calculating the offset of binary numbers (u,v) from the other value (t).
    Type: Grant
    Filed: November 10, 1987
    Date of Patent: July 18, 1989
    Assignee: International Business Machines Corporation
    Inventor: Arvind M. Patel
  • Patent number: 4833679
    Abstract: A method and apparatus is disclosed that is selectively conditionable, during read processing, to operate in normal or diagnostic on-the-fly mode or in normal or diagnostic deferred mode to correct errors in encoded uncorrected data in a disk storage device. During deferred mode operation, hardware in the disk storage device receives uncorrected data in real time and generates syndrome bytes which are decoded at the device into error pattern and error location information that is transmitted to a storage director. Circuitry is provided for retaining, if desired, error pattern and location information to facilitate identification of surface defects in the storage disk whether read processing was done on-the-fly or in deferred mode.
    Type: Grant
    Filed: August 31, 1987
    Date of Patent: May 23, 1989
    Assignee: International Business Machines Corporation
    Inventors: Robert W. Anderson, Ralph L. Gee, Jasper A. Indelicato, Arvind M. Patel
  • Patent number: 4804959
    Abstract: To increase storage capacity of a disk storage device, the recording surface of the device is partitioned into a plurality of concentric recording bands, data to be recorded on respective bands are encoded using different run-length-limited codes with the code rate of each band being higher than the adjacent inner band.
    Type: Grant
    Filed: November 10, 1987
    Date of Patent: February 14, 1989
    Assignee: International Business Machines Corporation
    Inventors: Tarek Makansi, Constantin M. Melas, Arvind M. Patel, Steven H. Souther
  • Patent number: 4786890
    Abstract: A rate 8/9, constrained partial response class IV code having run length limitation parameters (0,3/5) is provided for any partial response (PR) signaling system employing maximum likelihood (ML) detection.
    Type: Grant
    Filed: July 28, 1987
    Date of Patent: November 22, 1988
    Assignee: International Business Machines Corporation
    Inventors: Brian H. Marcus, Arvind M. Patel, Paul H. Siegel
  • Patent number: 4745604
    Abstract: In a data processing system in which two-level error correction is performed on variable length data being transferred between the host processor and the data storage device, the logical length of the data being transferred is computed during a fixed time gap with computation continuing after termination of the fixed time gap and commencement of the data transfer. The computation required for the logical length of the data field to accommodate two-level ECC is accomplished by first comparing the actual field length with a value predetermined by the subblock length of the two-level ECC. If the actual length is greater than the predetermined value, then a value equal to the subblock length plus first level ECC bytes is loaded into a counter which begins decrementing at the termination of the fixed time gap so as to synhronize by the byte-by-byte transfer of the data. As the data is being transferred the computation continues.
    Type: Grant
    Filed: October 20, 1986
    Date of Patent: May 17, 1988
    Assignee: International Business Machines Corporation
    Inventors: Arvind M. Patel, David T. Wang, Wellington C. Yu
  • Patent number: 4707681
    Abstract: Rate 8/9, constrained codes having run length limitation parameters (0, 4/4) and (0, 3/6) are provided for any partial response (PR) signalling system employing maximum likelihood (ML) detection.
    Type: Grant
    Filed: April 24, 1986
    Date of Patent: November 17, 1987
    Assignee: International Business Machines Corporation
    Inventors: John S. Eggenberger, Arvind M. Patel
  • Patent number: 4706250
    Abstract: A system for correcting errors in data read from a direct access storage device employs an extendable, two-level coding scheme having n subblocks in a relatively long variable-length block of data, each subblock having up to m bytes of data. At the subblock level, decoding capability provides correction of up to t.sub.1 errors and detection of up to t.sub.1 +c errors in each subblock, while the block-level decoding capability provides correction of up to t.sub.2 errors in any one of the subblocks. The combined capability of the system corrects any combination of (t.sub.1 +x) errors in one subblock, and up to t.sub.1 errors in any or all of the other subblocks in the block, where x is a non-negative integer such that (t.sub.1 +x).ltoreq.t.sub.2 and x<c. The combined capability of the system also provides correction of any combination of (t.sub.1 +x) errors in one subblock and up to (t.sub.1 +C-x) errors in any or all of the other subblocks in the block, where x is an integer such that (t.sub.1 +x).ltoreq.
    Type: Grant
    Filed: September 27, 1985
    Date of Patent: November 10, 1987
    Assignee: International Business Machines Corporation
    Inventor: Arvind M. Patel
  • Patent number: 4703485
    Abstract: Improved design, computation and implementation of pairs of error detection check bytes, where such bytes are appended to the end of a variable length record for data integrity check of the entire record after ECC correction, is provided. The error detection check bytes are each computed using different powers of the same companion T matrix of a degree-eight primitive polynomial used for computing associated ECC check bytes. Use of the same T matrix provides the computational convenience of a reasonable size Galois field of GF(2.sup.8), while providing long cycle length through a recurring offset within the data sequences corresponding to two members of each pair.
    Type: Grant
    Filed: February 10, 1986
    Date of Patent: October 27, 1987
    Assignee: International Business Machines Corporation
    Inventor: Arvind M. Patel
  • Patent number: 4525838
    Abstract: A two-level multibyte error correcting system is disclosed for correcting up to t.sub.1 one-byte errors in a codeword in response to processing 2t.sub.1 non-zero syndrome bytes at the first level and up to t.sub.2 one-byte errors in a codeword in response to processing 2t.sub.2 non-zero syndromes bytes at the second level when processing said 2t.sub.1 syndrome bytes at said first level does not produce an all zero pattern for said 2t.sub.2 syndrome bytes. A relatively long block of data may be divided into subblocks, each of which may contain up to t.sub.1 -x one-byte errors that are correctable at the first level by processing 2t.sub.1 non-zero syndrome bytes where one identifiable subblock of the word may contain up to t.sub.1 +x one-byte errors which are correctable by processing said 2t.sub.2 non-zero syndrome bytes where 0.ltoreq.x.ltoreq.(t.sub.2 -t.sub.1).
    Type: Grant
    Filed: February 28, 1983
    Date of Patent: June 25, 1985
    Assignee: International Business Machines Corporation
    Inventor: Arvind M. Patel