Patents by Inventor Asad Khamisy
Asad Khamisy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9141438Abstract: Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).Type: GrantFiled: February 22, 2013Date of Patent: September 22, 2015Inventors: Alexander Joffe, Asad Khamisy
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Publication number: 20140307740Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.Type: ApplicationFiled: June 27, 2014Publication date: October 16, 2014Inventors: Andrew Li, Michael Lau, Asad Khamisy
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Publication number: 20140245315Abstract: Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).Type: ApplicationFiled: February 22, 2013Publication date: August 28, 2014Inventors: Alexander Joffe, Asad Khamisy
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Patent number: 8806089Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.Type: GrantFiled: December 21, 2012Date of Patent: August 12, 2014Assignee: Net Navigation Systems, LLCInventors: Andrew Li, Michael Lau, Asad Khamisy
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Publication number: 20140025935Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.Type: ApplicationFiled: December 21, 2012Publication date: January 23, 2014Inventors: Andrew Li, Michael Lau, Asad Khamisy
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Patent number: 8387061Abstract: Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).Type: GrantFiled: June 30, 2011Date of Patent: February 26, 2013Inventors: Alexander Joffe, Asad Khamisy
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Patent number: 8370545Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.Type: GrantFiled: February 3, 2012Date of Patent: February 5, 2013Assignee: Net Navigation Systems, LLCInventors: Andrew Li, Michael Lau, Asad Khamisy
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Publication number: 20120134369Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.Type: ApplicationFiled: February 3, 2012Publication date: May 31, 2012Inventors: Andrew Li, Michael Lau, Asad Khamisy
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Patent number: 8135886Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.Type: GrantFiled: February 28, 2011Date of Patent: March 13, 2012Assignee: Net Navigation Systems, LLCInventors: Andrew Li, Michael Lau, Asad Khamisy
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Patent number: 8130648Abstract: A network device and method include token buckets, each token bucket associated with one of clients and virtual ports and configured to process information based on a predefined bandwidth and a strict priority/weighted deficit round robin. A maximum rate shaper module and a minimum rate meter module shape and meter whether any of the clients or virtual ports have exceeded a predefined threshold. A scheduler is configured to schedule services of the clients and to calculate a new bandwidth allocation for at least one of the clients or virtual ports when the at least one of the clients or virtual ports has exceeded the predefined threshold, the new bandwidth allocation replacing the predefined bandwidth and being proportional to the predefined bandwidth for each of the clients or virtual ports.Type: GrantFiled: December 21, 2006Date of Patent: March 6, 2012Assignee: Broadcom CorporationInventors: Bruce H. Kwan, Puneet Agarwal, Asad Khamisy
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Publication number: 20110265094Abstract: Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).Type: ApplicationFiled: June 30, 2011Publication date: October 27, 2011Inventors: Alexander Joffe, Asad Khamisy
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Patent number: 8001547Abstract: Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).Type: GrantFiled: August 29, 2008Date of Patent: August 16, 2011Assignee: Applied Micro Circuits CorporationInventors: Alexander Joffe, Asad Khamisy
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Publication number: 20110149989Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.Type: ApplicationFiled: February 28, 2011Publication date: June 23, 2011Inventors: Andrew Li, Michael Lau, Asad Khamisy
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Patent number: 7921241Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.Type: GrantFiled: June 1, 2009Date of Patent: April 5, 2011Assignee: Applied Micro Circuits CorporationInventors: Andrew Li, Michael Lau, Asad Khamisy
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Publication number: 20090240850Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.Type: ApplicationFiled: June 1, 2009Publication date: September 24, 2009Inventors: Andrew Li, Michael Lau, Asad Khamisy
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Patent number: 7558890Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.Type: GrantFiled: December 19, 2003Date of Patent: July 7, 2009Assignee: Applied Micro Circuits CorporationInventors: Andrew Li, Michael Lau, Asad Khamisy
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Publication number: 20080320485Abstract: Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).Type: ApplicationFiled: August 29, 2008Publication date: December 25, 2008Applicant: Applied Micro Circuits CorporationInventors: Alexander Joffe, Asad Khamisy
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Patent number: 7437535Abstract: This disclosure relates to communications among processors, coprocessors and memory. Specifically, a method and apparatus provide a single-cycle instruction (“store-and-load”) that stores a command to a co-processor to atomically process data and that loads resultant processed data.Type: GrantFiled: November 1, 2004Date of Patent: October 14, 2008Assignee: Applied Micro Circuits CorporationInventors: Alexander Joffe, Asad Khamisy
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Patent number: 7421693Abstract: Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).Type: GrantFiled: April 4, 2002Date of Patent: September 2, 2008Assignee: Applied Micro Circuits CorporationInventors: Alexander Joffe, Asad Khamisy
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Publication number: 20070153697Abstract: A network device and method include token buckets, each token bucket associated with one of clients and virtual ports and configured to process information based on a predefined bandwidth and a strict priority/weighted deficit round robin. A maximum rate shaper module and a minimum rate meter module shape and meter whether any of the clients or virtual ports have exceeded a predefined threshold. A scheduler is configured to schedule services of the clients and to calculate a new bandwidth allocation for at least one of the clients or virtual ports when the at least one of the clients or virtual ports has exceeded the predefined threshold, the new bandwidth allocation replacing the predefined bandwidth and being proportional to the predefined bandwidth for each of the clients or virtual ports.Type: ApplicationFiled: December 21, 2006Publication date: July 5, 2007Inventors: Bruce H. Kwan, Puneet Agarwal, Asad Khamisy