Patents by Inventor Ashay Dani
Ashay Dani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260206653Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for hybrid bonding a die to a substrate. In embodiments, the die may be a chiplet that is bonded to an interconnect. In embodiments, the die may be a plurality of dies, where the plurality of dies are hybrid bonded to a substrate, to each other, or a combination of both. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 10, 2026Publication date: July 16, 2026Inventors: Hongxia FENG, Xiaoxuan SUN, Amey Anant APTE, Dingying David XU, Sairam AGRAHARAM, Gang DUAN, Ashay DANI
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Patent number: 12642130Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for hybrid bonding a die to a substrate. In embodiments, the die may be a chiplet that is bonded to an interconnect. In embodiments, the die may be a plurality of dies, where the plurality of dies are hybrid bonded to a substrate, to each other, or a combination of both. Other embodiments may be described and/or claimed.Type: GrantFiled: March 30, 2022Date of Patent: May 26, 2026Assignee: Intel CorporationInventors: Hongxia Feng, Xiaoxuan Sun, Amey Anant Apte, Dingying David Xu, Sairam Agraharam, Gang Duan, Ashay Dani
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Publication number: 20250279384Abstract: Methods and apparatus using polymer material to fill gaps between semiconductor dies are disclosed. An example apparatus comprises a semiconductor substrate, a semiconductor die positioned on the semiconductor substrate, and a polymer material in contact with a side of the semiconductor die, the polymer material extending from a first surface of the semiconductor die towards a second surface of the semiconductor die, the first surface of the semiconductor die facing towards the semiconductor substrate and the second surface of the semiconductor die facing away from the semiconductor substrate.Type: ApplicationFiled: February 29, 2024Publication date: September 4, 2025Inventors: Hongxia Feng, Trianggono Widodo, Radha Malini Gowri Muddu, Elizabeth Nofen, Mohit Gupta, Jose Fernando Waimin Almendares, Dingying Xu, Ashay Dani, Leonel Arana, Xavier F. Brun, Houri Johari-Galle, Sairam Agraharam, Nitin Deshpande
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Publication number: 20250218999Abstract: Embodiments disclosed herein include passive electrical components with thickness modifications. In an embodiment, such an apparatus may comprise a first substrate with a first material composition, where the first substrate comprises a passive electrical device. In an embodiment, a second substrate is coupled to the first substrate, where the second substrate has a second material composition. In an embodiment, a layer is over a surface of the second substrate opposite from the first substrate, and the layer is electrically insulating.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Inventors: Bohan SHAN, Hongxia FENG, Jose WAIMIN, Ryan CARRAZZONE, Kyle ARRINGTON, Ziyin LIN, Dingying David XU, Yongki MIN, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Wei LI, Ashay DANI, Leonel R. ARANA, Brandon C. MARIN, Clay ARRINGTON, Hiroki TANAKA, Haobo CHEN, Mohit GUPTA
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Publication number: 20250218958Abstract: Pedestals for semiconductors embedded in package substrates and related methods are disclosed. An example package substrate for an integrated circuit package disclosed herein includes core having a first surface, a second surface, and a cavity formed in the first surface, a semiconductor component disposed in the cavity, and a pedestal disposed in the cavity, the pedestal having a third surface coupled to the semiconductor component, and a fourth surface adjacent to the first surface, the pedestal dimensioned such that a first thickness of the pedestal and semiconductor is substantially equal to a second thickness of the core.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Inventors: Brandon Christian Marin, Bohan Shan, Joseph Allen Van Nausdle, Leonel Arana, Kyle Jordan Arrington, Xavier F. Brun, Ryan Joseph Carrazzone, Ashay Dani, Gang Duan, Hongxia Feng, Mohit Gupta, Wei Li, Ziyin Lin, Yongki Min, Tyler Osborn, Srinivas Venkata Ramanuja Pietambaram, Teng Sun, Jose Fernando Waimin Almendares, Dingying Xu
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Publication number: 20250218998Abstract: Embodiments disclosed herein include an apparatus that comprises a first substrate and a second substrate over the first substrate. In an embodiment, an array of interconnects is provided between the first substrate and the second substrate. The array of interconnects comprises a first interconnect with a first material composition, and a second interconnect with a second material composition that is different than the first material composition.Type: ApplicationFiled: December 29, 2023Publication date: July 3, 2025Inventors: Bohan SHAN, Shripad GOKHALE, Rui ZHANG, Mine KAYA, Haobo CHEN, Steve S. CHO, Timothy GOSSELIN, Kartik SRINIVASAN, Edvin CETEGEN, Kyle ARRINGTON, Nicholas S. HAEHN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Ashay DANI, Yoshihiro TOMITA, Ziyin LIN, Yiqun BAI, Jose WAIMIN, Dingying David XU, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Jung Kyu HAN, Liang HE
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Publication number: 20250218926Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a substrate having a material and conductive pathways through the material, wherein the material includes an organic dielectric material; and a microelectronic component having a first surface and an opposing second surface, wherein the first surface of the microelectronic component is electrically coupled to the conductive pathways in the material by interconnects, wherein the interconnects include solder and are surrounded by a capillary underfill material, and wherein the microelectronic component and the capillary underfill material are surrounded by the material of the substrate.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Minglu Liu, Bohan Shan, Ziyin Lin, Haobo Chen, Yiqun Bai, Kyle Jordan Arrington, Jose Waimin, Ryan Carrazzone, Hongxia Feng, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Dingying Xu, Bin Mu, Mohit Gupta, Jeremy Ecton, Brandon C. Marin, Xiaoying Guo, Ashay Dani, Yosuke Kanaoka
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Publication number: 20250112085Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface of the cavity, and build-up layers formed over the organic dielectric material around the integrated circuit bridge device. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Bohan Shan, Ziyin Lin, Haobo Chen, Yiqun Bai, Kyle Arrington, Jose Waimin, Ryan Carrazzone, Hongxia Feng, Dingying Xu, Srinivas Pietambaram, Minglu Liu, Seyyed Yahya Mousavi, Xinyu Li, Gang Duan, Wei Li, Bin Mu, Mohit Gupta, Jeremy Ecton, Brandon C. Marin, Xiaoying Guo, Ashay Dani
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Publication number: 20250112136Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Bohan SHAN, Jesse JONES, Zhixin XIE, Bai NIE, Shaojiang CHEN, Joshua STACEY, Mitchell PAGE, Brandon C. MARIN, Jeremy D. ECTON, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Edvin CETEGEN, Jason M. GAMBA, Jacob VEHONSKY, Jianyong MO, Makoyi WATSON, Shripad GOKHALE, Mine KAYA, Kartik SRINIVASAN, Haobo CHEN, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Hiroki TANAKA, Ashay DANI, Praveen SREERAMAGIRI, Yi LI, Ibrahim EL KHATIB, Aaron GARELICK, Robin MCREE, Hassan AJAMI, Yekan WANG, Andrew JIMENEZ, Jung Kyu HAN, Hanyu SONG, Yonggang Yong LI, Mahdi MOHAMMADIGHALENI, Whitney BRYKS, Shuqi LAI, Jieying KONG, Thomas HEATON, Dilan SENEVIRATNE, Yiqun BAI, Bin MU, Mohit GUPTA, Xiaoying GUO
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Publication number: 20250106983Abstract: Embodiments disclosed herein include glass core package substrates with a stiffener. In an embodiment, an apparatus comprises a substrate with a first layer with a first width, where the first layer is a glass layer, a second layer under the first layer, where the second layer has a second width that is smaller than the first width, and a third layer over the first layer, where the third layer has a third width that is smaller than the first width. In an embodiment, the apparatus further comprises a metallic structure with a first portion and a second portion, where the first portion is over a top surface of the substrate and the second portion extends away from the first portion and covers at least a sidewall of the first layer.Type: ApplicationFiled: September 27, 2023Publication date: March 27, 2025Inventors: Bohan SHAN, Kyle ARRINGTON, Dingying David XU, Ziyin LIN, Timothy GOSSELIN, Elah BOZORG-GRAYELI, Aravindha ANTONISWAMY, Wei LI, Haobo CHEN, Yiqun BAI, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Ashay DANI
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Publication number: 20240222301Abstract: Methods and apparatus for optical thermal treatment in semiconductor packages are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, an interconnect associated with the dielectric substrate, and light absorption material proximate or surrounding the interconnect, the light absorption material to increase in temperature in response to being exposed to a pulsed light for thermal treatment corresponding to the IC package.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Inventors: Bohan Shan, Hongxia Feng, Haobo Chen, Srinivas Pietambaram, Bai Nie, Gang Duan, Kyle Arrington, Ziyin Lin, Yiqun Bai, Xiaoying Guo, Dingying Xu, Sairam Agraharam, Ashay Dani, Eric J. M. Moret, Tarek Ibrahim
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Publication number: 20240222283Abstract: Methods and apparatus to prevent over-etch in semiconductor packages are disclosed. A disclosed example semiconductor package includes at least one dielectric layer, an interconnect extending at least partially through or from the at least one dielectric layer, and a material on at least a portion of the interconnect, wherein the material comprises at least one of silicon or titanium.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Inventors: Hongxia Feng, Bohan Shan, Bai Nie, Xiaoxuan Sun, Holly Sawyer, Tarek Ibrahim, Adwait Telang, Dingying Xu, Leonel Arana, Xiaoying Guo, Ashay Dani, Sairam Agraharam, Haobo Chen, Srinivas Pietambaram, Gang Duan
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Publication number: 20230317653Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for hybrid bonding a die to a substrate. In embodiments, the die may be a chiplet that is bonded to an interconnect. In embodiments, the die may be a plurality of dies, where the plurality of dies are hybrid bonded to a substrate, to each other, or a combination of both. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Hongxia FENG, Xiaoxuan SUN, Amey Anant APTE, Dingying David XU, Sairam AGRAHARAM, Gang DUAN, Ashay DANI
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Publication number: 20200203067Abstract: The inductor includes a plurality of inductive elements that are at least partially encapsulated, covered, or embedded in a composite magnetic material that improves the inductance of the inductor without a corresponding, detrimental, increase in the size of the inductor. The composite magnetic material includes a plurality of magnetic particles dispersed in a carrier medium. Each of the magnetic particles includes a magnetic core that is encapsulated in a dielectric magnetic coating. The dielectric magnetic coating is a thermally stable material having high electrical resistivity.Type: ApplicationFiled: September 29, 2017Publication date: June 25, 2020Applicant: Intel CorporationInventors: Malavarayan Sankarasubramanian, Yongki Min, Ashay Dani
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Patent number: 9247686Abstract: Embodiments of the present invention provide various polymeric matrices that may be used as a binder matrix for polymer solder hybrid thermal interface materials. In alternative embodiments the binder matrix material may be phophozene, perfluoro ether, polyether, or urethane. For one embodiment, the binder matrix is selected to provide improved adhesion to a variety of interfaces. For an alternative embodiment the binder matrix is selected to provide low contact resistance. In alternative embodiments, polymeric materials containing fusible and non-fusible particles may be used in application where heat removal is desired and is not restricted to thermal interface materials for microelectronic devices.Type: GrantFiled: March 5, 2014Date of Patent: January 26, 2016Assignee: Intel CorporationInventors: Saikumar Jayaraman, Paul A. Koning, Ashay Dani
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Publication number: 20140182763Abstract: Embodiments of the present invention provide various polymeric matrices that may be used as a binder matrix for polymer solder hybrid thermal interface materials. In alternative embodiments the binder matrix material may be phophozene, perfluoro ether, polyether, or urethane. For one embodiment, the binder matrix is selected to provide improved adhesion to a variety of interfaces. For an alternative embodiment the binder matrix is selected to provide low contact resistance. In alternative embodiments, polymeric materials containing fusible and non-fusible particles may be used in application where heat removal is desired and is not restricted to thermal interface materials for microelectronic devices.Type: ApplicationFiled: March 5, 2014Publication date: July 3, 2014Inventors: Saikumar JAYARAMAN, Paul A. KONING, Ashay DANI
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Patent number: 8703286Abstract: Embodiments of the present invention provide various polymeric matrices that may be used as a binder matrix for polymer solder hybrid thermal interface materials. In alternative embodiments the binder matrix material may be phophozene, perfluoro ether, polyether, or urethane. For one embodiment, the binder matrix is selected to provide improved adhesion to a variety of interfaces. For an alternative embodiment the binder matrix is selected to provide low contact resistance. In alternative embodiments, polymeric materials containing fusible and non-fusible particles may be used in application where heat removal is desired and is not restricted to thermal interface materials for microelectronic devices.Type: GrantFiled: April 20, 2011Date of Patent: April 22, 2014Assignee: Intel CorporationInventors: Saikumar Jayaraman, Paul A. Koning, Ashay Dani
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Publication number: 20110194254Abstract: Embodiments of the present invention provide various polymeric matrices that may be used as a binder matrix for polymer solder hybrid thermal interface materials. In alternative embodiments the binder matrix material may be phophozene, perfluoro ether, polyether, or urethane. For one embodiment, the binder matrix is selected to provide improved adhesion to a variety of interfaces. For an alternative embodiment the binder matrix is selected to provide low contact resistance. In alternative embodiments, polymeric materials containing fusible and non-fusible particles may be used in application where heat removal is desired and is not restricted to thermal interface materials for microelectronic devices.Type: ApplicationFiled: April 20, 2011Publication date: August 11, 2011Inventors: Saikumar Jayaraman, Paul A. Koning, Ashay Dani
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Patent number: 7967942Abstract: Embodiments of the present invention provide various polymeric matrices that may be used as a binder matrix for polymer solder hybrid thermal interface materials. In alternative embodiments the binder matrix material may be phophozene, perfluoro ether, polyether, or urethane. For one embodiment, the binder matrix is selected to provide improved adhesion to a variety of interfaces. For an alternative embodiment the binder matrix is selected to provide low contact resistance. In alternative embodiments, polymeric materials containing fusible and non-fusible particles may be used in application where heat removal is desired and is not restricted to thermal interface materials for microelectronic devices.Type: GrantFiled: July 6, 2007Date of Patent: June 28, 2011Assignee: Intel CorporationInventors: Saikumar Jayaraman, Paul A. Koning, Ashay Dani
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Patent number: 7960019Abstract: An electronic assembly having a microelectronic die, a heat spreader and a heat sink. A first thermal interface material is disposed between the microelectronic die and the heat spreader. A second thermal interface material is disposed between the heat spreader and a heat sink. The first and second interface materials each comprising a phase change polymer, a solderable material and a plurality of thermally conductive non-fusible particles. The solderable material interconnecting the non-fusible particles to form a plurality of columnar structures within the phase change polymer.Type: GrantFiled: August 15, 2007Date of Patent: June 14, 2011Assignee: Intel CorporationInventors: Salkumar Jayaraman, Paul A. Koning, Ashay Dani
