Patents by Inventor Ashish Agrawal

Ashish Agrawal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11132448
    Abstract: Methods, apparatus, and processor-readable storage media for encryption using wavelet transformation are provided herein. An example computer-implemented method includes generating a modified item of cryptographic information by randomly incorporating one or more characters into a user-provided item of cryptographic information; converting the modified item of cryptographic information to a matrix code; creating multiple bands of data by applying wavelet transformation to the matrix code; generating one or more encrypted items of cryptographic information by converting a selected one of the multiple bands of data into a sequence of multiple characters by applying an encoding process to the selected band of data; and storing the encrypted items of cryptographic information in a database for use in authentication requests.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: September 28, 2021
    Assignee: Dell Products L.P.
    Inventors: Sathish Bikumala, Siddharth Agrawal, Ashish Kumar Palo
  • Patent number: 11106345
    Abstract: Disclosed are various approaches for connecting third-party services for user interaction. A user can select content on a user interface associated with a first third-party service. The content can be associated with a second third-party service. A client application can transmit the content to an integrated service over a network in a request to obtain additional information from the second third-party service. The integrated service can transmit the additional information to the client application. The user interface can be modified to include a user interface element containing the information associated with the second third-party service.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: August 31, 2021
    Assignee: VMware, Inc.
    Inventors: Shree Harsha Shedigumme, Sudharsan Thumatti Sathiamoorthy, Amit Jain, Ashish Agrawal, Sharun Varghese Samuel, Shaleen Mittal
  • Publication number: 20210202378
    Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Inventors: Gilbert Dewey, Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady, Anand Murthy
  • Publication number: 20210202319
    Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include monocrystalline source and drain material epitaxially grown from a monocrystalline channel material at a temperature low enough to avoid degradation of a lower level transistor structure and/or degradation of one or more low-k dielectric materials between the transistor levels. A highly conductive n-type silicon source and drain material may be selectively deposited at low temperatures with a high pressure CVD process. Multiple crystals of source drain material arranged in a vertically stacked multi-channel transistor structure may be contacted by a single contact metallization.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Applicant: Intel Corporation
    Inventors: Ashish Agrawal, Gilbert Dewey, Cheng-Ying Huang, Willy Rachmady, Anand Murthy, Ryan Keech, Cory Bomberger
  • Publication number: 20210202476
    Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Inventors: Cheng-Ying Huang, Gilbert Dewey, Ashish Agrawal, Kimin Jun, Willy Rachmady, Zachary Geiger, Cory Bomberger, Ryan Keech, Koustav Ganguly, Anand Murthy, Jack Kavalieros
  • Patent number: 11031499
    Abstract: An apparatus including a transistor device including a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel includes a length dimension between source and drain that is greater than a length dimension of the gate electrode such that there is a passivated underlap between an edge of the gate electrode and an edge of the channel relative to each of the source and the drain. A method including forming a channel of a transistor device on a substrate; forming first and second passivation layers on a surface of substrate on opposite sides of the channel; forming a gate stack on the channel between first and second passivation layers; and forming a source on the substrate between the channel and the first passivation layer and a drain on the substrate between the channel and the second passivation layer.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Van H. Le, Matthew V. Metz, Benjamin Chu-Kung, Ashish Agrawal, Jack T. Kavalieros
  • Patent number: 11024713
    Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region of doped semiconductor material on the substrate adjacent a second side of the semiconductor region, and a transition region in the drain region, adjacent the semiconductor region, wherein the transition region comprises varying dopant concentrations that increase in a direction away from the semiconductor region. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Dipanjan Basu, Glenn A. Glass, Harold W. Kennel, Ashish Agrawal, Benjamin Chu-Kung, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 11018075
    Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Carl Naylor, Ashish Agrawal, Kevin Lin, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan
  • Patent number: 11010822
    Abstract: A computer process enables a target window associated with a first domain to receive a message from a child window associated with a second domain. The message is passed using an iframe that is created within the target window. The process may, for example, be used to relay information entered by a user into the child window to the target window.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: May 18, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Hendi Chandi, Ashish Agrawal, Dhanvi H. Kapila, Vineesh Sinha
  • Patent number: 10998270
    Abstract: Techniques are disclosed for forming transistor devices having reduced interfacial resistance in a local interconnect. The local interconnect can be a material having similar composition to that of the source/drain material. That composition can be a metal alloy of a group IV element such as nickel germanide. The local interconnect of the semiconductor integrated circuit can function in the absence of barrier and liner layers. The devices can be used on MOS transistors including PMOS transistors.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Glenn A. Glass, Van H. Le, Ashish Agrawal, Benjamin Chu-Kung, Anand S. Murthy, Jack T. Kavalieros
  • Patent number: 10985263
    Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Dipanjan Basu, Ashish Agrawal, Van H. Le, Benjamin Chu-Kung, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20210050455
    Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.
    Type: Application
    Filed: October 19, 2020
    Publication date: February 18, 2021
    Inventors: Van H. LE, Gilbert DEWEY, Rafael RIOS, Jack T. KAVALIEROS, Marko RADOSAVLJEVIC, Kent E. MILLARD, Marc C. FRENCH, Ashish AGRAWAL, Benjamin CHU-KUNG, Ryan E. ARCH
  • Publication number: 20210036023
    Abstract: Thin film transistor structures may include a regrown source or drain material between a channel material and source or drain contact metallization. The source or drain material may be selectively deposited at low temperatures to backfill recesses formed in the channel material. Electrically active dopant impurities may be introduced in-situ during deposition of the source or drain material. The source or drain material may overlap a portion of a gate electrode undercut by the recesses. With channel material of a first composition and source or drain material of a second composition, thin film transistor structures may display low external resistance and high channel mobility.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Ashish Agrawal, Jack Kavalieros, Anand Murthy, Gilbert Dewey, Matthew Metz, Willy Rachmady, Cheng-Ying Huang, Cory Bomberger
  • Publication number: 20210019707
    Abstract: Disclosed are various approaches for workflow service email integration. In some examples, a request is transmitted to a workflow service. The request includes workflow content associated with an email message being composed. A workflow micro application associated with the workflow content is received form the workflow service. The workflow micro application is generated using network service data retrieved from a network service. The workflow micro application includes: an information component that renders the network service data for display within the email message. The workflow micro application also includes an evaluation component that evaluates a management status of a client device.
    Type: Application
    Filed: August 27, 2019
    Publication date: January 21, 2021
    Inventors: Sudharsan Thumatti Sathiamoorthy, Rohit Pradeep Shetty, Shree Harsha S, Ashish Agrawal, Amit Jain
  • Patent number: 10884766
    Abstract: Disclosed are various approaches for connecting third-party services for user interaction. An integration service can receive from a client device a content query including a selection of content by a user interacting with a user interface on the client device. The integration service can compare the content query with predefined connector data to identify a connector associated with the content query. The integration service can send the content query and an authentication token of the user to the connector to access information from a third-party service. In response to receiving the information from the third-party service, the integration service can provide the information to the client device.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 5, 2021
    Assignee: VMWARE, INC.
    Inventors: Shree Harsha Shedigumme, Sudharsan Thumatti Sathiamoorthy, Amit Jain, Ashish Agrawal, Sharun Varghese Samuel, Shaleen Mittal
  • Patent number: 10847656
    Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Van H. Le, Gilbert Dewey, Rafael Rios, Jack T. Kavalieros, Marko Radosavljevic, Kent E. Millard, Marc C. French, Ashish Agrawal, Benjamin Chu-Kung, Ryan E. Arch
  • Publication number: 20200335610
    Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.
    Type: Application
    Filed: February 28, 2018
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Cheng-Ying Huang, Jack Kavalieros, Ian Young, Matthew Metz, Willy Rachmady, Uygar Avci, Ashish Agrawal, Benjamin Chu-Kung
  • Publication number: 20200313001
    Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Ryan KEECH, Benjamin CHU-KUNG, Subrina RAFIQUE, Devin MERRILL, Ashish AGRAWAL, Harold KENNEL, Yang CAO, Dipanjan BASU, Jessica TORRES, Anand MURTHY
  • Patent number: 10784352
    Abstract: Related fields of the present disclosure are in the field of transistor devices, and in particular, FinFET device structures formed using aspect ratio trapping trench (ART) process techniques. For example, a FinFET device consistent with the present disclosure comprises a first fin structure including a first upper fin portion atop a first lower fin portion and a second fin structure including a second upper fin portion atop a second lower fin portion. The first and second upper fin structures include a Group IV material and the first and second lower fin structures include a Group III-V material.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Sanaz K. Gardner, Willy Rachmady, Van H. Le, Matthew V. Metz, Seiyon Kim, Ashish Agrawal, Jack T. Kavalieros
  • Publication number: 20200293185
    Abstract: Disclosed are various approaches for connecting third-party services for user interaction. A user can select content on a user interface associated with a first third-party service. The content can be associated with a second third-party service. A client application can transmit the content to an integrated service over a network in a request to obtain additional information from the second third-party service. The integrated service can transmit the additional information to the client application. The user interface can be modified to include a user interface element containing the information associated with the second third-party service.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Inventors: Shree Harsha Shedigumme, Sudharsan Thumatti Sathiamoorthy, Amit Jain, Ashish Agrawal, Sharun Varghese Samuel, Shaleen Mittal