Patents by Inventor Ashish Gupta

Ashish Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080155990
    Abstract: An apparatus including a socket having a socket body and a cavity within the socket body. The apparatus further including a thermoelectric cooler coupled to an in-substrate voltage regulator positioned within the cavity. A method including coupling a thermoelectric cooler to an in-substrate voltage regulator positioned within a cavity of a socket and electrically coupling the thermoelectric cooler to the socket using a contact of the socket. A system including an electronic appliance having a processor including an in-substrate voltage regulator positioned within a cavity of a socket coupled to the processor. The system further including a thermoelectric cooler positioned within the cavity and coupled to the in-substrate voltage regulator.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 3, 2008
    Inventors: Ashish Gupta, David S. Chau
  • Publication number: 20080155537
    Abstract: Certain embodiments of the present invention provide systems and method for automatic inference and adaptation of a virtualized computer environment. Certain embodiments of a system include a virtual topology and traffic inference framework tool adapted to monitor traffic for an application on a virtual network to produce a view of network demands for the application. The system also includes a monitoring tool adapted to monitor performance of an underlying physical network associated with the virtual network using traffic for the application. Further, the system includes an adaptation component adapted to automatically adapt the application to the virtual network based on the measured application traffic, the monitored network performance, and one or more adaptation control algorithms.
    Type: Application
    Filed: July 24, 2007
    Publication date: June 26, 2008
    Inventors: Peter Dinda, Ananth Sundararaj, John Lange, Ashish Gupta, Bin Lin
  • Patent number: 7376775
    Abstract: In some embodiments, an apparatus includes a processor, an expander memory bridge location, a memory coupled to the expander memory bridge location, and a bus controller including intercept logic to intercept and block communication from the processor to the expander memory bridge location and to emulate an expander memory bridge. In some embodiments, a method includes intercepting and blocking a status request to a device, regardless of whether the device is installed, and responding to the status request.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: May 20, 2008
    Assignee: Intel Corporation
    Inventors: Lily Pao Looi, Stanley Steven Kulick, Dean A Mulla, Ashish Gupta, Keith R. Pflederer, Shivnandan D. Kaushik, Mohan J. Kumar, James B. Crossland
  • Patent number: 7366098
    Abstract: A method is described that resets a first count and resets a second count if a first transmission unit is recognized as being within a new measurement time window. The first transmission unit has a size. The method also increments the first count by the first transmission unit size and by the size of each subsequent transmission unit that is received within the new measurement time window after the first transmission unit—so long as the first count does not exceed a maximum allowable value for the first count. The method also checks if a maximum value for the second count is exceeded if it is incremented by a second transmission unit size. The second transmission unit is received within the measurement time window. The check is in response to a determination that the first count would have exceeded the first count maximum allowable valuable if the first count were incremented by the second transmission unit size.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: April 29, 2008
    Assignee: Cisco Technology, Inc.
    Inventors: Raja Rangarjan, Ashish Gupta, Rohit Sharma, Naresh Kumar Sharma, Frederic Mathieu, Jayakumar Jayakumar
  • Patent number: 7328375
    Abstract: An example computer system includes a first bridge device that includes an interface controller. The interface controller combines debug information generated within the bridge device with a training pattern. The first bridge device is coupled to a second bridge device via a high-speed asynchronous interconnect. The first bridge device converts the debug information and training pattern into a packet to be transmitted over the interconnect to the second bridge device. The training pattern serves to allow the second bridge device to maintain bit and symbol synchronization during the transfer; of the debug information.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: February 5, 2008
    Assignee: Intel Corporation
    Inventors: Ashish Gupta, Bahaa Fahim, Kent Dickey, Jonathan Jasper
  • Publication number: 20080002365
    Abstract: In some embodiments, socket enabled cooling of in-substrate voltage regulator is presented. In this regard, a socket is introduced having a socket body with a substantially central cavity, a plurality of contacts through the socket body arranged in a substantially square pattern around the cavity, and an integrated heat spreader substantially covering the cavity. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 3, 2008
    Inventor: Ashish Gupta
  • Patent number: 7249273
    Abstract: Some embodiments provide a synchronization circuit to receive a synchronization signal, the synchronization signal substantially synchronized with a data transition, to synchronize the synchronization signal with a clock signal, and to generate a load signal based on the synchronized synchronization signal. Also provided may be a ring counter to receive the load signal from the synchronization circuit and to circularly propagate the load signal.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: July 24, 2007
    Assignee: Intel Corporation
    Inventors: Chengting Zhao, Ashish Gupta, Edward R. Helder, Fangxing Wei
  • Publication number: 20060224748
    Abstract: The claimed system is a service support framework for a multicast programming system implemented on top of a service oriented framework, specifically a service oriented messaging system.
    Type: Application
    Filed: March 15, 2005
    Publication date: October 5, 2006
    Applicant: MICROSOFT CORPORATION
    Inventors: Ashish Gupta, Jeremy Dewey, Padmini Iyer, Ravi Rao
  • Publication number: 20060212582
    Abstract: The claimed system is a multicast programming model for implementation on top of a service oriented framework, specifically a service oriented messaging system. It provides application-layer multicast capability without requiring an IP multicast infrastructure.
    Type: Application
    Filed: March 15, 2005
    Publication date: September 21, 2006
    Applicant: MICROSOFT CORPORATION
    Inventors: Ashish Gupta, Jeremy Dewey, Padmini Iyer, Ravi Rao
  • Publication number: 20060212592
    Abstract: The claimed method and system is an API set to support a multicast programming or implementation on top of a service oriented framework, specifically a service messaging system.
    Type: Application
    Filed: March 15, 2005
    Publication date: September 21, 2006
    Applicant: MICROSOFT CORPORATION
    Inventors: Ashish Gupta, Jeremy Dewey, Padmini Iyer, Ravi Rao, Todd Manion
  • Patent number: 7103728
    Abstract: A distributed-memory multi-processor system includes a plurality of cells communicatively coupled to each other and collectively including a plurality of processors, caches, main memories, and cell controllers. Each of the cells includes at least one of the processors, at least one of the caches, one of the main memories, and one of the cell controllers. Each of the cells is configured to perform memory migration functions for migrating memory from a first one of the main memories to a second one of the main memories in a manner that is invisible to an operating system of the system.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: September 5, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Debendra Das Sharma, Ashish Gupta, William R. Bryg
  • Publication number: 20060064372
    Abstract: The present invention generally relates to a single transaction account identifier that can be used for in transactions with one of multiple transaction accounts. The method includes one or more of the following steps: establishing at least two transaction accounts, wherein the transaction accounts are respectively associated with transaction account identifiers; receiving, at a transaction processing system, a common account identifier; recognizing the common account identifier as being associated with more than one account; and determining, which of the at least two transaction accounts to access for processing the transaction. The determining step may be based on selection criteria and the selection criteria may be modified by a user. One of the first and second transaction account identifiers may be forwarded to the respective first and second transaction accounts based on the determining step; and the transaction may be processed via the selected transaction account.
    Type: Application
    Filed: September 8, 2004
    Publication date: March 23, 2006
    Applicant: AMERICAN EXPRESS TRAVEL RELATED SERVICES COMPANY, INC.
    Inventor: Ashish Gupta
  • Publication number: 20050171861
    Abstract: A method and system for allowing users of different web pages to exchange information. The information exchange system identifies groups of related web pages and maintains a database of user-supplied information for each group of related web pages. When a user accesses a web page the information exchange often displays in a separate area the information associated with the group of related web pages. Also the information exchange system allows the user to enter information that will be displayed to other users who access related web pages.
    Type: Application
    Filed: March 28, 2005
    Publication date: August 4, 2005
    Inventors: Jeffrey Bezos, Ashish Gupta
  • Publication number: 20050149314
    Abstract: In some embodiments, an apparatus includes a processor, an expander memory bridge location, a memory coupled to the expander memory bridge location, and a bus controller including intercept logic to intercept and block communication from the processor to the expander memory bridge location and to emulate an expander memory bridge. In some embodiments, a method includes intercepting and blocking a status request to a device, regardless of whether the device is installed, and responding to the status request.
    Type: Application
    Filed: December 29, 2003
    Publication date: July 7, 2005
    Inventors: Lily Looi, Stanley Kulick, Dean Mulla, Ashish Gupta, Keith Pflederer, Shivnandan Kaushik, Mohan Kumar, James Crossland
  • Publication number: 20050149705
    Abstract: An example computer system includes a first bridge device that includes an interface controller. The interface controller combines debug information generated within the bridge device with a training pattern. The first bridge device is coupled to a second bridge device via a high-speed asynchronous interconnect. The first bridge device converts the debug information and training pattern into a packet to be transmitted over the interconnect to the second bridge device. The training pattern serves to allow the second bridge device to maintain bit and symbol synchronization during the transfer; of the debug information.
    Type: Application
    Filed: December 30, 2003
    Publication date: July 7, 2005
    Inventors: Ashish Gupta, Bahaa Fahim, Kent Dickey, Jonathan Jasper
  • Publication number: 20050102305
    Abstract: Relational database applications such as index selection, histogram tuning, approximate query processing, and statistics selection have recognized the importance of leveraging workloads. Often these applications are presented with large workloads, i.e., a set of SQL DML statements, as input. A key factor affecting the scalability of such applications is the size of the workload. The invention concerns workload compression which helps improve the scalability of such applications. The exemplary embodiment is broadly applicable to a variety of workload-driven applications, while allowing for incorporation of application specific knowledge. The process is described in detail in the context of two workload-driven applications: index selection and approximate query processing.
    Type: Application
    Filed: December 8, 2004
    Publication date: May 12, 2005
    Applicant: Microsoft Corporation
    Inventors: Surajit Chaudhuri, Ashish Gupta, Vivek Narasayya, Sanjay Agrawal
  • Patent number: 6889250
    Abstract: A method and system for allowing users of different web pages to exchange information. The information exchange system identifies groups of related web pages and maintains a database of user-supplied information for each group of related web pages. When a user accesses a web page, the information exchange often displays in a separate area the information associated with the group of related web pages. Also, the information exchange system allows the user to enter information that will be displayed to other users who access related web pages.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: May 3, 2005
    Assignee: Amazon.com, Inc.
    Inventors: Jeffrey P. Bezos, Ashish Gupta
  • Patent number: 6874070
    Abstract: A method of accessing a plurality of memories in an interleaved manner using a contiguous logical address space includes providing at least one map table. The at least one map table includes a plurality of entries. Each entry includes a plurality of entry items. Each entry item identifies one of the memories. A first logical address is received. The first logical address includes a plurality of address bits. The plurality of address bits includes a first set of address bits corresponding to a first set of entries in the at least one map table. A first entry in the first set of entries is identified based on the first set and a second set of the address bits. A first entry item in the first entry is identified based on a third set of the address bits. The memory identified by the first entry item is accessed.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: March 29, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ashish Gupta, William R. Bryg
  • Publication number: 20040260961
    Abstract: Some embodiments provide a synchronization circuit to receive a synchronization signal, the synchronization signal substantially synchronized with a data transition, to synchronize the synchronization signal with a clock signal, and to generate a load signal based on the synchronized synchronization signal. Also provided may be a ring counter to receive the load signal from the synchronization circuit and to circularly propagate the load signal.
    Type: Application
    Filed: June 23, 2003
    Publication date: December 23, 2004
    Inventors: Chengting Zhao, Ashish Gupta, Edward R. Helder, Fangxing Wei
  • Patent number: 6832270
    Abstract: A virtual input/output (I/O) interconnect mechanism, and a corresponding method, for use in a computer system having a plurality of I/O devices and a plurality of processing units, where I/O devices and processing units are coupled by one or more bridge units, includes an address decode block having a multiplexer that multiplexes inputs to produce an address, where the address relates to a transaction related to a processor unit, a range register decoder that receives the address and provides a destination address of a module to receive the transaction related to the address, and a reroute module identification block that receives the destination address.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: December 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Debendra Das Sharma, Ashish Gupta