Patents by Inventor Ashish Jagmohan

Ashish Jagmohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8230217
    Abstract: A method and system provide for secure sharing of arbitrary data between users with limited mutual trust. A user can encode its information by using a Slepian-Wolf code at a rate which enables a second user to correctly decode only if the side-information it has satisfies a conditional entropy constraint. The key advantages are as follows. Firstly, it is very flexible, in that it enables secure sharing for general data including multimedia data. Secondly, by appropriate Slepian-Wolf code selection, it enables compression in conjunction with security. Thirdly, it can be used for the case where the data model is imperfectly known and trust is to be built up incrementally.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: July 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Dake He, Ashish Jagmohan, Ligang Lu
  • Publication number: 20120144249
    Abstract: Program disturb error logging and correction for a flash memory including a computer implemented method for storing data. The method includes receiving a write request that includes data and a write address of a target page in a memory. A previously programmed page at a specified offset from the target page is read from the memory. Contents of the previously programmed page are compared to an expected value of the previously programmed page. Error data is stored in an error log in response to contents of the previously programmed page being different than the expected value of the previously programmed page, the error data describing an error in the previously programmed page and the error data used by a next read operation to the previously programmed page to correct the error in the previously programmed page. The received data is written to the target page in the memory.
    Type: Application
    Filed: December 3, 2010
    Publication date: June 7, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michele M. Franceschini, Ashish Jagmohan
  • Publication number: 20120144272
    Abstract: Error correction in not-and (NAND) flash memory including a system for retrieving data from memory. The system includes a decoder in communication with a memory. The decoder is for performing a method that includes receiving a codeword stored on a page in the memory, the codeword including data and first-tier check symbols that are generated in response to the data. The method further includes determining that the codeword includes errors that cannot be corrected using the first-tier check symbols, and in response second-tier check symbols are received. The second-tier check symbols are generated in response to receiving the data and to the contents of other pages in the memory that were written prior to the page containing the codeword. The codeword is corrected in response to the second-tier check symbols. The corrected codeword is output.
    Type: Application
    Filed: December 3, 2010
    Publication date: June 7, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michele M. Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano, Mayank Sharma
  • Patent number: 8176235
    Abstract: Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, and for determining if the number of free bits in the invalid previously written memory page at the selected physical address is greater than or equal to the data rate. The memory system also includes a transmitter for outputting the selected physical address of the invalid previously written memory page, the outputting in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: May 8, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michele M. Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano, Mayank Sharma
  • Patent number: 8176234
    Abstract: Multi-write coding of non-volatile memories including a method that receives write data, and a write address of a memory page. The memory page is in either an erased state or a previously written state. If the memory page is in the erased state: selecting a first codeword from a code such that the first codeword encodes the write data and is consistent with a target set of distributions of electrical charge levels in the memory page; and writing the first codeword to the memory page. If the memory page is in the previously written state: selecting a coset from a linear code such that the coset encodes the write data and includes one or more words that are consistent with previously written content of the memory page; selecting a subsequent codeword from the one or more words in the coset; and writing the subsequent codeword to the memory page.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: May 8, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michele M. Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano
  • Publication number: 20120096328
    Abstract: Multi-write endurance and error control coding of non-volatile memories including a method for receiving write data and a write address of a memory page in a memory. The write data is partitioned into a plurality of sub-blocks, each sub-block including q bits of the write data. Error correction bits are generated at the computer in response to the sub-blocks and to an error correction code (ECC). At least one additional sub-block containing the error correction bits are appended to the partitioned write data and a write word is generated. The write word is generated by performing for each of the sub-blocks: selecting a codeword such that the codeword encodes the sub-block and is consistent with current electrical charge levels of the plurality of memory cells associated with the memory page; concatenating the selected codewords to form the write word; and writing the write word to the memory page.
    Type: Application
    Filed: October 13, 2010
    Publication date: April 19, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michele M. Franceschini, Ashish Jagmohan
  • Patent number: 8160130
    Abstract: The present invention relates to a method, system and computer program product for the predictive encoding of digital video sequences. The objectives of the invention are accomplished by dynamically determining the resolution of a current frame being encoded and outputting the determination. The determination process is based on statistical and coding information of a plurality of frames, including at least one previous frame and the current frame. Further, general encoding parameters and the encoding parameters of a current frame at a chosen resolution are determined, wherein the encoding parameter selection step takes into account the determination of the dynamic resolution determination step in determining the encoding parameters.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: April 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Krishna C. Ratakonda, Ashish Jagmohan
  • Patent number: 8111755
    Abstract: A method and system for low-complexity Slepian-Wolf rate estimator in a hybrid Wyner-Ziv video encoder determines the minimum Slepian-Wolf code rate required to allow correct decoding. The Slepian-Wolf estimator does not assume ideality of source and side-information statistics and does not require the presence of a feedback channel from the decoder to the encoder in order to determine the correct Slepian-Wolf coding rate. Instead, it adapts to the statistical properties of the video steam. The Slepian-Wolf estimator provides very efficient compression performance while avoiding Slepian-Wolf decoding failures.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: February 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Dake He, Ashish Jagmohan
  • Publication number: 20110320881
    Abstract: Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John S. Dodson, Frank D. Ferraiolo, Michele M. Franceschini, Kevin C. Gower, Lisa C. Gower, Ashish Jagmohan, Luis A. Lastras-Montano, Kenneth L. Wright
  • Publication number: 20110307670
    Abstract: Encoding data into constrained memory using a method for writing data that includes receiving write data to be encoded into a write word, receiving constraints on symbol values associated with the write word, encoding the write data into the write word, and writing the write word to a memory. The encoding includes: representing the write data and the constraints as a first linear system in a first field of a first size; embedding the first linear system into a second linear system in a second field of a second size, the second size larger than the first size; solving the second linear system in the second field resulting in a solution; and collapsing the solution into the first field resulting in the write word, the write word satisfying the constraints on symbol values associated with the write word.
    Type: Application
    Filed: June 11, 2010
    Publication date: December 15, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michele M. Franceshini, Ashish Jagmohan, Luis A. Lastras-Montano, Mayank Sharma
  • Publication number: 20110246703
    Abstract: Constrained coding to reduce floating gate coupling in non-volatile memories including a method for storing data. The method includes receiving write data to be written to a flash memory device, selecting a codeword in response to the write data, and writing the codeword to the flash memory device. The codeword is selected to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword.
    Type: Application
    Filed: March 31, 2010
    Publication date: October 6, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michele M. Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano, Mayank Sharma
  • Publication number: 20110206145
    Abstract: Methods and apparatus are provided for secure distribution and storage of data using N channels. An input data sequence, X, is distributed using a plurality, N, of channels. In one embodiment, the input data sequence, X, is split into N subsequences; and the N subsequences are encoded into N bit streams using a set of Slepian-Wolf codes with N separate encoders and a joint decoder. The Slepian-Wolf codes can be selected to ensure a computational complexity to obtain a portion of the input data sequence grows exponentially with respect to a length of the input data sequence unless all of the N bit streams are compromised. In another embodiment, the input data sequence, X, is compressed using a lossless data compressing techniques; and the compressed input data sequence is split into N subsequences that are distributed.
    Type: Application
    Filed: February 25, 2010
    Publication date: August 25, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ligang Lu, Ashish Jagmohan, Dake He
  • Publication number: 20110187565
    Abstract: A method, system and computer program product are disclosed for rateless compression of non-binary sources. In one embodiment, the method comprises representing a sequence of non-binary source symbols as a sequence of sets of binary values; selecting a code for compressing the sets of binary values; determining a puncturing pattern, based on the selected code; and puncturing the sets of binary values, in patterns based on the puncturing pattern, to form a sequence of unpunctured values. A sequence of computed syndromes is determined based on the sequence of non-binary source symbols; and the sequence of unpunctured values and the sequence of computed syndromes are combined to form an output stream of data representing said sequence of non-binary source symbols. In one embodiment, none of the sets of binary values is punctured completely, and, for example, each of the sets of binary values may be punctured only partially.
    Type: Application
    Filed: February 3, 2010
    Publication date: August 4, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ashish Jagmohan, Demijan Klinc
  • Patent number: 7990290
    Abstract: A method, system and computer program product are disclosed for rateless compression of non-binary sources. In one embodiment, the method comprises representing a sequence of non-binary source symbols as a sequence of sets of binary values; selecting a code for compressing the sets of binary values; determining a puncturing pattern, based on the selected code; and puncturing the sets of binary values, in patterns based on the puncturing pattern, to form a sequence of unpunctured values. A sequence of computed syndromes is determined based on the sequence of non-binary source symbols; and the sequence of unpunctured values and the sequence of computed syndromes are combined to form an output stream of data representing said sequence of non-binary source symbols. In one embodiment, none of the sets of binary values is punctured completely, and, for example, each of the sets of binary values may be punctured only partially.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: August 2, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ashish Jagmohan, Demijan Klinc
  • Publication number: 20110138104
    Abstract: Multi-write coding of non-volatile memories including a method that receives write data, and a write address of a memory page. The memory page is in either an erased state or a previously written state. If the memory page is in the erased state: selecting a first codeword from a code such that the first codeword encodes the write data and is consistent with a target set of distributions of electrical charge levels in the memory page; and writing the first codeword to the memory page. If the memory page is in the previously written state: selecting a coset from a linear code such that the coset encodes the write data and includes one or more words that are consistent with previously written content of the memory page; selecting a subsequent codeword from the one or more words in the coset; and writing the subsequent codeword to the memory page.
    Type: Application
    Filed: December 4, 2009
    Publication date: June 9, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michele M. Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano
  • Publication number: 20110138105
    Abstract: Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, and for determining if the number of free bits in the invalid previously written memory page at the selected physical address is greater than or equal to the data rate. The memory system also includes a transmitter for outputting the selected physical address of the invalid previously written memory page, the outputting in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate.
    Type: Application
    Filed: December 4, 2009
    Publication date: June 9, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michele M. Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano, Mayank Sharma
  • Patent number: 7945842
    Abstract: A method of and system for rateless source coding are disclosed. The method comprises the steps of providing a set of low-density parity check (LDPC) codes, each of which accepts a range of data input lengths and a range of target compression rates; identifying a data input having a data input length; and identifying a desired compression rate. The method comprises the further steps of selecting one of said LDPC codes based on said data input length and desired compression rate; encoding the data input, using the selected LDPC code, to generate a sequence of data values; and puncturing some of said encoded data values to achieve the desired compression rate. Preferably, the encoding step includes the steps of generating a syndrome and a parity sequence from the data input, puncturing the generated parity sequence, and mixing a remaining portion of the data input with the punctuated parity sequence.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: May 17, 2011
    Assignee: International Business Machines Corporation
    Inventors: Dake He, Ashish Jagmohan, Jing Jiang
  • Publication number: 20110103580
    Abstract: A method, system and computer program product are disclosed for compressing encrypted data, wherein the data is encrypted by using a block encryption algorithm in a chained mode of operation, and the encrypted data is comprised of a set of N encrypted blocks, C1 . . . CN. In one embodiment, the method comprises leaving block CN uncompressed, and compressing all of the blocks C1 . . . CN in a defined sequence using a Slepian-Wolf code. In an embodiment, the data is encrypted using an encryption key K, and the compressing includes compressing all of the blocks C1 . . . CN without using the encryption key. In one embodiment, the compressing includes outputting the blocks C1 . . . CN as a set of compressed blocks CmprC1 . . . CmprCN-1, and the method further comprises decrypting CN to generate a reconstructed block {tilde over (X)}n, and decrypting and decompressing the set of compressed blocks using {tilde over (X)}n.
    Type: Application
    Filed: November 2, 2009
    Publication date: May 5, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Camit Hazay, Ashish Jagmohan, Demijan Klinc, Hugo M. Krawczyk, Tal Rabin
  • Patent number: 7894550
    Abstract: A method and apparatus for decompressing data in a data-compression system with decoder-only side information is provided. In one aspect, the method comprises generating side information using a source reconstruction and decoding using the generated side information to generate a new source reconstruction. The method further includes iterating the steps of generating and decoding, the generating step using at least the new source reconstruction output by the previous decoding step, and the decoding step using the side information output by the previous generating step. The method may stop the iteration when one or more predetermined criteria are met.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Dake He, Ashish Jagmohan, Ligang Lu, Vadim Sheinin
  • Publication number: 20110019002
    Abstract: A method of and system for signal analysis includes acquiring multiple signals from the environment by using multiple sensor elements, applying a transform which combines the multiple acquired signals into a single combined signal, and reduces the number of samples in the combined signal, applying a single signal analysis and event detection operation on the resultant combined, sparse signal, and performing a complete signal analysis using multiple analysis elements for the multiple input signals only in the case where the sparse signal analysis indicates that the event of interest may be present.
    Type: Application
    Filed: July 22, 2009
    Publication date: January 27, 2011
    Applicant: International Business Machines Corporation
    Inventors: Ashish Jagmohan, Vadim Sheinin