Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

Abstract: A method for detecting early life failure of an electrical connection of a power harness for a steering system of a vehicle including, using a processor configured to execute instructions, obtaining a resistance measurement associated with an electrical power delivery system including the electrical connection, obtaining historical resistance data obtaining at least one limit based on at least one of the historical resistance data and a functional limit, detecting an early life failure of the electrical connection based on a comparison between the resistance measurement and the at least one limit, performing at least one action in response to detecting the early life failure.

Abstract: A method for detecting degradation intermittencies in an electrical connection in a steering system of a vehicle includes, using a processor configured to execute instructions, receiving an input indicative of a plurality of measurements of resistance associated with the electrical connection, calculating, based on the received input, at least one adaptive control threshold, comparing a first measurement of the plurality of measurements to the at least one adaptive control threshold, determining whether the electrical connection has a degradation intermittency in response to the comparison between the first measurement and the at least one adaptive control threshold, and performing at least one action in response to determining that the electrical connection has the degradation intermittency.

Abstract: A method for determining a state of health (SOH) of an electrical connection in a steering system includes, using a processor configured to execute instructions, receiving an input indicative of the SOH of the electrical connection, the input including a resistance associated with the electrical connection, and the SOH corresponding to at least one of an accumulated health (AH) of the electrical connection and a remaining usable life (RUL) of the electrical connection, calculating, based on the received input and usage associated with the vehicle, a first SOH value, calculating, based on the received input and behavior associated with the vehicle, a second SOH value, calculating, based on the first SOH value and the second SOH value, a third SOH value, the third SOH value being an indicator of the AH or the RUL of the electrical connection, and performing at least one action based on the third SOH value.

Abstract: Integrated circuit (IC) devices and systems with backside power gates, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with one or more transistors, a first interconnect over the device layer, a second interconnect under the device layer, and one or more power gates under the device layer.

Abstract: Techniques and mechanisms for providing gate dielectric structures of a transistor. In an embodiment, the transistor comprises a thin channel structure which comprises one or more layers of a transition metal dichalcogenide (TMD) material. The channel structure forms two surfaces on opposite respective sides thereof, wherein the surfaces extend to each of two opposing edges of the channel structure. A composite gate dielectric structure comprises first bodies of a first dielectric material, wherein the first bodies each adjoin a different respective one of the two opposing edges, and variously extend to each of the surfaces two surfaces. The composite gate dielectric structure further comprises another body of a second dielectric material other than the first dielectric material. In another embodiment, the other body adjoins one or both of the two surfaces, and extends along one or both of the two surfaces to each of the first bodies.

Abstract: Methods for doping 2D transistor devices and resulting architectures. The use and placement of oxide dopants, such as, but not limited to, GeOx, enable control over threshold voltage performance and contact resistance of 2D transistor devices. Architectures include distinct stoichiometry compositions.

Abstract: A transistor includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source structure coupled to a first end of the first and second channel layers, a drain structure coupled to a second end of the first and second channel layers, a gate structure between the source material and the drain material, and between the first channel layer and the second channel layer. The transistor further includes a spacer laterally between the gate structure and the and the source structure and between the gate structure and the drain structure. A liner is between the spacer and the gate structure. The liner is in contact with the first channel layer and the second channel layer and extends between the gate structure and the respective source structure and the drain structure.

Abstract: Transistor structures with monocrystalline metal chalcogenide channel materials are formed from a plurality of template regions patterned over a substrate. A crystal of metal chalcogenide may be preferentially grown from a template region and the metal chalcogenide crystals then patterned into the channel region of a transistor. The template regions may be formed by nanometer-dimensioned patterning of a metal precursor, a growth promoter, a growth inhibitor, or a defected region. A metal precursor may be a metal oxide suitable, which is chalcogenated when exposed to a chalcogen precursor at elevated temperature, for example in a chemical vapor deposition process.

Abstract: Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.

Abstract: Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region.

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.

Abstract: A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source material coupled to a first end of the first and second channel layers, a drain material coupled to a second end of the first and second channel layers, a gate electrode between the source material and the drain material, and between the first channel layer and the second channel layer and a gate dielectric between the gate electrode and each of the first channel layer and the second channel layer.

Abstract: A memory device structure includes a transistor structure including a gate electrode over a top surface of a fin and adjacent to a sidewall of the fin, a source structure coupled to a first region of the fin and a drain structure coupled to a second region of the fin, where the gate electrode is between the first and the second region. A gate dielectric layer is between the fin and the gate electrode. The memory device structure further includes a capacitor coupled with the transistor structure, the capacitor includes the gate electrode, a ferroelectric layer on a substantially planar uppermost surface of the gate electrode and a word line on the ferroelectric layer.

Abstract: Systems and techniques that facilitate participant selection in federated learning are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory that can execute the computer executable components stored in memory. The computer executable components can comprise a clustering component that clusters one or more participants in a federated learning system based on distributions of data classification labels for data sets of the one or more participants into one or more clusters of participants; and a selection component that selects participants equitably from across the one or more clusters of participants for a round of federated learning.

Abstract: A method for determining motor velocity includes receiving motor sensor data from at least one motor sensor associated with an electric motor, the motor sensor data including a plurality of motor sensor measurements and respective time values; determining an average time value based on the respective time values for each motor sensor measurement; generating a first gain value, a second gain value, and a third gain value, the first gain value being generated based on at least the average time value; and estimating a motor velocity based on at least one motor sensor measurement, the average time value, the first gain value, the second gain value, the third gain value, and at least one previously estimated motor velocity.

Abstract: A method, computer system, and a computer program product for classification training are provided. A deep learning model is trained with a first dataset that includes annotated samples that include a first and second class. Last hidden state features corresponding to respective tokens from prototypes of the first and second class are saved. The trained deep learning model is further trained with a second dataset that includes additional annotated samples that include the first and second class and a third class. The further training includes performing a cosine similarity loss optimization and a cross entropy loss optimization. The cosine similarity loss optimization is of last hidden state features resulting from the further trained deep learning model and the first class and the second class compared to the saved last hidden state features. The cross entropy loss optimization is for classification of the first, second, and the third class.

Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.

Abstract: A transistor includes a channel including a first layer including a first monocrystalline transition metal dichalcogenide (TMD) material, where the first layer is stoichiometric and includes a first transition metal. The channel further includes a second layer above the first layer, the second layer including a second monocrystalline TMD material, where the second monocrystalline TMD material includes a second transition metal and oxygen, and where the second layer is sub-stoichiometric. The transistor further includes a gate electrode above a first portion of the channel layer, a gate dielectric layer between the channel layer and the gate electrode, a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate electrode is between drain contact and the source contact.

Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.