Patents by Inventor Ashish Verma
Ashish Verma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240222482Abstract: Devices, transistor structures, systems, and techniques are described herein related to field effect transistors having a doping layer on metal chalcogenide nanoribbons outside of the channel region. The doping layer is a metal oxide that shifts the electrical characteristics of the nanoribbons and is formed by depositing a metal and oxidizing the metal by exposure to ozone and ultraviolet light.Type: ApplicationFiled: December 29, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Kevin P. O'Brien, Rachel Steinhardt, Chelsey Dorow, Carl H. Naylor, Kirby Maxey, Sudarat Lee, Ashish Verma Penumatcha, Uygar Avci, Scott Clendenning, Tristan Tronic, Mahmut Sami Kavrik, Ande Kitamura
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Publication number: 20240222461Abstract: A transistor in an integrated circuit (IC) die includes source and drain terminals having a bulk material enclosed by a liner material. A nanoribbon channel region couples the source and drain terminals. The nanoribbon may include a transition metal and a chalcogen. The liner material may contact ends and upper and lower surfaces of the nanoribbon. The transistor may be in an interconnect layer. The source and drain terminals may be formed by conformally depositing the liner material over the ends of the nanoribbon and in voids opened in the IC die.Type: ApplicationFiled: December 29, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Ande Kitamura, Carl H. Naylor, Kevin O'Brien, Kirby Maxey, Chelsey Dorow, Ashish Verma Penumatcha, Scott B. Clendenning, Uygar Avci, Matthew Metz, Chia-Ching Lin, Sudarat Lee, Mahmut Sami Kavrik, Carly Rogan, Paul Gutwin
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Publication number: 20240222428Abstract: A transistor has multiple channel regions coupling source and drain structures, and a seed material is between one of the source or drain structures and a channel material, which includes a metal and a chalcogen. Each channel region may include a nanoribbon. A nanoribbon may have a monocrystalline structure and a thickness of a monolayer, less than 1 nm. A nanoribbon may be free of internal grain boundaries. A nanoribbon may have an internal grain boundary adjacent an end opposite the seed material. The seed material may directly contact the first of the source or drain structures, and the channel material may directly contact the second of the source or drain structures.Type: ApplicationFiled: December 29, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Chelsey Dorow, Carl H. Naylor, Kirby Maxey, Kevin O'Brien, Ashish Verma Penumatcha, Chia-Ching Lin, Uygar Avci, Matthew Metz, Sudarat Lee, Ande Kitamura, Scott B. Clendenning, Mahmut Sami Kavrik
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Publication number: 20240222483Abstract: A transistor structure includes a stack of nanoribbons spanning between terminals of the transistor. Ends of the nanoribbons include silicon, and channel regions between the ends include a transition metal and a chalcogen. A gate structure over the channel regions includes an insulator between the channel regions and a gate electrode material. Contact regions may be formed by modifying portions of the channel regions by adding a dopant to, or altering the crystal structure of, the channel regions. The transistor structure may be in an integrated circuit device.Type: ApplicationFiled: December 29, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Carl H. Naylor, Kirby Maxey, Kevin O’Brien, Chelsey Dorow, Sudarat Lee, Ashish Verma Penumatcha, Uygar Avci, Matthew Metz, Scott B. Clendenning, Chia-Ching Lin, Ande Kitamura, Mahmut Sami Kavrik
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Publication number: 20240222113Abstract: Integrated circuit (IC) structures comprising transistors with metal chalcogenide channel material synthesized on a workpiece comprising a Group IV crystal. Prior to synthesis of the metal chalcogenide material, a passivation material is formed over the Group IV crystal to limit exposure of the substrate to the growth precursor gas(es) and thereby reduce a quantity of chalcogen species subsequently degassed from the workpiece. The passivation material may be applied to the front side, back side, and/or edge of a workpiece. The passivation material may be sacrificial or retained as a permanent feature of an IC structure. The passivation material may be advantageously amorphous and/or a compound comprising at least one of a metal or nitrogen that is good diffusion barrier and thermally stable at the metal chalcogenide synthesis temperatures.Type: ApplicationFiled: December 29, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Carl H. Naylor, Kirby Maxey, Kevin OBrien, Chelsey Dorow, Sudarat Lee, Ashish Verma Penumatcha, Uygar Avci, Matthew Metz, Scott B. Clendenning, Mahmut Sami Kavrik, Chia-Ching Lin, Ande Kitamura
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Publication number: 20240222484Abstract: Transistors and integrated circuitry including a 2D channel material layer within a stack of material layers further including one or more insulator (e.g., dielectric) materials above and/or below the 2D channel material layer. These supporting insulator layers may be non-sacrificial while other material layers within a starting material stack may be sacrificial, replaced, for example, with gate insulator and/or gate material. In some exemplary embodiments, the 2D channel material is a metal chalcogenide and the supporting insulator layer is advantageously a dielectric material composition having a low dielectric constant.Type: ApplicationFiled: December 30, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Chia-Ching Lin, Kevin P. O'Brien, Ashish Verma Penumatcha, Chelsey Dorow, Kirby Maxey, Carl H. Naylor, Tao Chu, Guowei Xu, Uygar Avci, Feng Zhang, Ting-Hsiang Hung, Ande Kitamura, Mahmut Sami Kavrik
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Publication number: 20240186416Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.Type: ApplicationFiled: January 16, 2024Publication date: June 6, 2024Inventors: Kevin P. O'Brien, Carl NAYLOR, Chelsey DOROW, Kirby MAXEY, Tanay GOSAVI, Ashish Verma PENUMATCHA, Shriram SHIVARAMAN, Chia-Ching LIN, Sudarat LEE, Uygar E. AVCI
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Patent number: 11980037Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.Type: GrantFiled: June 19, 2020Date of Patent: May 7, 2024Assignee: Intel CorporationInventors: Nazila Haratipour, Shriram Shivaraman, Sou-Chi Chang, Jack T. Kavalieros, Uygar E. Avci, Chia-Ching Lin, Seung Hoon Sung, Ashish Verma Penumatcha, Ian A. Young, Devin R. Merrill, Matthew V. Metz, I-Cheng Tung
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Patent number: 11974189Abstract: A computer-implemented method enables registered mobile device users associated with a common matter to identify each other in a court-complex setting, and to communicate with each other directly using mobile devices once the registered mobile device users enter a code associated to the common matter. A server-side application receives and processes user and/or firm names to effect registration. Using the mobile device application, a first registered mobile device user enters a code associated with the common matter, received by the server-side application that receives and processes the code, effecting check in by the first registered mobile device user. Using the mobile application, a second registered user enters the code associated with the common matter, enabling the first and second registered mobile device user associated with the common matter to communicate over a wireless network using Voice over Internet Protocol (VoIP), Wi-Fi and/or cellular telephony.Type: GrantFiled: February 10, 2022Date of Patent: April 30, 2024Inventors: Richard Joseph Sullivan, Ashish Verma
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Patent number: 11941520Abstract: Techniques regarding determining hyperparameters for a differentially private federated learning process are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a hyperparameter advisor component that determines a hyperparameter for a model of a differentially private federated learning process based on a defined numeric relationship between a privacy budget, a learning rate schedule, and a batch size.Type: GrantFiled: January 9, 2020Date of Patent: March 26, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Colin Sutcher-Shepard, Ashish Verma, Jayaram Kallapalayam Radhakrishnan, Gegi Thomas
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Patent number: 11935956Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.Type: GrantFiled: June 26, 2020Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Kevin P. O'Brien, Carl Naylor, Chelsey Dorow, Kirby Maxey, Tanay Gosavi, Ashish Verma Penumatcha, Shriram Shivaraman, Chia-Ching Lin, Sudarat Lee, Uygar E. Avci
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Publication number: 20240079980Abstract: A method for determining motor velocity includes receiving motor sensor data from at least one motor sensor associated with an electric motor, the motor sensor data including a plurality of motor sensor measurements and respective time values; determining an average time value based on the respective time values for each motor sensor measurement; generating a first gain value, a second gain value, and a third gain value, the first gain value being generated based on at least the average time value; and estimating a motor velocity based on at least one motor sensor measurement, the average time value, the first gain value, the second gain value, the third gain value, and at least one previously estimated motor velocity.Type: ApplicationFiled: September 4, 2022Publication date: March 7, 2024Inventors: Nicholas Gizinski, Julie A. Kleinau, Ashish Verma
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Patent number: 11908950Abstract: Embodiments include two-dimensional (2D) semiconductor sheet transistors and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of 2D semiconductor sheets, where individual ones of the 2D semiconductor sheets have a first end and a second end opposite from the first end. In an embodiment, a first spacer is over the first end of the 2D semiconductor sheets, and a second spacer is over the second end of the 2D semiconductor sheets. Embodiments further comprise a gate electrode between the first spacer and the second spacer, a source contact adjacent to the first end of the 2D semiconductor sheets, and a drain contact adjacent to the second end of the 2D semiconductor sheets.Type: GrantFiled: June 15, 2020Date of Patent: February 20, 2024Assignee: Intel CorporationInventors: Kirby Maxey, Chelsey Dorow, Kevin P. O'Brien, Carl Naylor, Ashish Verma Penumatcha, Tanay Gosavi, Uygar E. Avci, Shriram Shivaraman
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Patent number: 11901400Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.Type: GrantFiled: March 29, 2019Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Nazila Haratipour, Chia-Ching Lin, Sou-Chi Chang, Ashish Verma Penumatcha, Owen Loh, Mengcheng Lu, Seung Hoon Sung, Ian A. Young, Uygar Avci, Jack T. Kavalieros
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Publication number: 20240047939Abstract: A distributed feedback plus reflection (DFB+R) laser includes an active section, a passive section, a low reflection (LR) mirror, and an etalon. The active section includes a distributed feedback (DFB) grating and is configured to operate in a lasing mode. The passive section is coupled end to end with the active section. The LR mirror is formed on or in the passive section. The etalon includes a portion of the DFB grating, the passive section, and the LR mirror. The lasing mode of the active section is aligned to a long-wavelength edge of a reflection peak of the etalon.Type: ApplicationFiled: August 4, 2022Publication date: February 8, 2024Inventors: Yasuhiro Matsui, Ashish Verma, Martin Kwakernaak
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Patent number: 11892519Abstract: Technical solutions are described for diagnosing an input power supply providing power to a motor. A method includes: generating a sinusoidal stimulus signal; applying, using the input power supply, the sinusoidal stimulus signal to the motor; measuring a response to the sinusoidal stimulus signal; determining a degraded condition of the input power supply based on the response to the sinusoidal stimulus signal; and performing an action in response to determining the degraded condition of the input power supply.Type: GrantFiled: April 29, 2022Date of Patent: February 6, 2024Assignee: Steering Solutions IP Holding CorporationInventors: Nicholas E. Gizinski, Julie A. Kleinau, David M. Williams, Clayton D. Larson, Steven J. Collier-Hallman, Ashish Verma
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Publication number: 20240006521Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that may be used as access transistors for a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Chia-Ching LIN, Shriram SHIVARAMAN, Kevin P. O'BRIEN, Ashish Verma PENUMATCHA, Chelsey DOROW, Kirby MAXEY, Carl H. NAYLOR, Sudarat LEE, Uygar E. AVCI
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Publication number: 20240006484Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a channel with a first end and a second end opposite from the first end, a first spacer around the first end of the channel, a second spacer around the second end of the channel, and a gate stack over the channel, where the gate stack is between the first spacer and the second spacer. In an embodiment, the transistor may further comprise a first extension contacting the first end of the channel; and a second extension contacting the first end of the channel. In an embodiment, the transistor further comprises conductive layers over the first extension and the second extension outside of the first spacer and the second spacer.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Ashish Verma PENUMATCHA, Kevin P. O'BRIEN, Kirby MAXEY, Carl H. NAYLOR, Chelsey DOROW, Uygar E. AVCI, Matthew V. METZ, Sudarat LEE, Chia-Ching LIN, Sean T. MA
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Publication number: 20240008290Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that include a metal-ferroelectric-metal-insulator-semiconductor structure used as a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Chia-Ching LIN, Shriram SHIVARAMAN, Kevin P. O'BRIEN, Ashish Verma PENUMATCHA, Chelsey DOROW, Kirby MAXEY, Carl H. NAYLOR, Sudarat LEE, Uygar E. AVCI, Sou-Chi CHANG
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Patent number: D1020142Type: GrantFiled: June 3, 2022Date of Patent: March 26, 2024Assignee: Electrolux Home Products, Inc.Inventors: Ashish Verma, Rathish Kumar