Abstract: A method for determining motor velocity includes receiving motor sensor data from at least one motor sensor associated with an electric motor, the motor sensor data including a plurality of motor sensor measurements and respective time values; determining an average time value based on the respective time values for each motor sensor measurement; generating a first gain value, a second gain value, and a third gain value, the first gain value being generated based on at least the average time value; and estimating a motor velocity based on at least one motor sensor measurement, the average time value, the first gain value, the second gain value, the third gain value, and at least one previously estimated motor velocity.

Abstract: A method, computer system, and a computer program product for classification training are provided. A deep learning model is trained with a first dataset that includes annotated samples that include a first and second class. Last hidden state features corresponding to respective tokens from prototypes of the first and second class are saved. The trained deep learning model is further trained with a second dataset that includes additional annotated samples that include the first and second class and a third class. The further training includes performing a cosine similarity loss optimization and a cross entropy loss optimization. The cosine similarity loss optimization is of last hidden state features resulting from the further trained deep learning model and the first class and the second class compared to the saved last hidden state features. The cross entropy loss optimization is for classification of the first, second, and the third class.

Abstract: A transistor includes a channel including a first layer including a first monocrystalline transition metal dichalcogenide (TMD) material, where the first layer is stoichiometric and includes a first transition metal. The channel further includes a second layer above the first layer, the second layer including a second monocrystalline TMD material, where the second monocrystalline TMD material includes a second transition metal and oxygen, and where the second layer is sub-stoichiometric. The transistor further includes a gate electrode above a first portion of the channel layer, a gate dielectric layer between the channel layer and the gate electrode, a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate electrode is between drain contact and the source contact.

Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.

Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.

Abstract: A system, computer program product, and method are presented for performing multi-objective automated machine learning, and, more specifically, to identifying a plurality of machine learning pipelines as Pareto-optimal solutions to optimize a plurality of objectives. The method includes receiving input data directed toward one or more subjects of interest and determining a plurality of objectives to be optimized. The method also includes ingesting at least a portion of the input data through one or more machine learning (ML) models. The method further includes aggregating the plurality of objectives into one or more aggregated single objectives. The method also includes determining a plurality of Pareto-optimal solutions, thereby defining a plurality of ML pipelines that optimize the one or more aggregated single objectives. The method further includes selecting one ML pipeline from the plurality of ML pipelines.

Abstract: A transistor has multiple channel regions coupling source and drain structures, and a seed material is between one of the source or drain structures and a channel material, which includes a metal and a chalcogen. Each channel region may include a nanoribbon. A nanoribbon may have a monocrystalline structure and a thickness of a monolayer, less than 1 nm. A nanoribbon may be free of internal grain boundaries. A nanoribbon may have an internal grain boundary adjacent an end opposite the seed material. The seed material may directly contact the first of the source or drain structures, and the channel material may directly contact the second of the source or drain structures.

Abstract: A transistor structure includes a stack of nanoribbons spanning between terminals of the transistor. Ends of the nanoribbons include silicon, and channel regions between the ends include a transition metal and a chalcogen. A gate structure over the channel regions includes an insulator between the channel regions and a gate electrode material. Contact regions may be formed by modifying portions of the channel regions by adding a dopant to, or altering the crystal structure of, the channel regions. The transistor structure may be in an integrated circuit device.

Abstract: Devices, transistor structures, systems, and techniques are described herein related to field effect transistors having a doping layer on metal chalcogenide nanoribbons outside of the channel region. The doping layer is a metal oxide that shifts the electrical characteristics of the nanoribbons and is formed by depositing a metal and oxidizing the metal by exposure to ozone and ultraviolet light.

Abstract: Transistors and integrated circuitry including a 2D channel material layer within a stack of material layers further including one or more insulator (e.g., dielectric) materials above and/or below the 2D channel material layer. These supporting insulator layers may be non-sacrificial while other material layers within a starting material stack may be sacrificial, replaced, for example, with gate insulator and/or gate material. In some exemplary embodiments, the 2D channel material is a metal chalcogenide and the supporting insulator layer is advantageously a dielectric material composition having a low dielectric constant.

Abstract: A transistor in an integrated circuit (IC) die includes source and drain terminals having a bulk material enclosed by a liner material. A nanoribbon channel region couples the source and drain terminals. The nanoribbon may include a transition metal and a chalcogen. The liner material may contact ends and upper and lower surfaces of the nanoribbon. The transistor may be in an interconnect layer. The source and drain terminals may be formed by conformally depositing the liner material over the ends of the nanoribbon and in voids opened in the IC die.

Abstract: Integrated circuit (IC) structures comprising transistors with metal chalcogenide channel material synthesized on a workpiece comprising a Group IV crystal. Prior to synthesis of the metal chalcogenide material, a passivation material is formed over the Group IV crystal to limit exposure of the substrate to the growth precursor gas(es) and thereby reduce a quantity of chalcogen species subsequently degassed from the workpiece. The passivation material may be applied to the front side, back side, and/or edge of a workpiece. The passivation material may be sacrificial or retained as a permanent feature of an IC structure. The passivation material may be advantageously amorphous and/or a compound comprising at least one of a metal or nitrogen that is good diffusion barrier and thermally stable at the metal chalcogenide synthesis temperatures.

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

Abstract: A computer-implemented method enables registered mobile device users associated with a common matter to identify each other in a court-complex setting, and to communicate with each other directly using mobile devices once the registered mobile device users enter a code associated to the common matter. A server-side application receives and processes user and/or firm names to effect registration. Using the mobile device application, a first registered mobile device user enters a code associated with the common matter, received by the server-side application that receives and processes the code, effecting check in by the first registered mobile device user. Using the mobile application, a second registered user enters the code associated with the common matter, enabling the first and second registered mobile device user associated with the common matter to communicate over a wireless network using Voice over Internet Protocol (VoIP), Wi-Fi and/or cellular telephony.

Abstract: Techniques regarding determining hyperparameters for a differentially private federated learning process are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a hyperparameter advisor component that determines a hyperparameter for a model of a differentially private federated learning process based on a defined numeric relationship between a privacy budget, a learning rate schedule, and a batch size.

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

Abstract: A method for determining motor velocity includes receiving motor sensor data from at least one motor sensor associated with an electric motor, the motor sensor data including a plurality of motor sensor measurements and respective time values; determining an average time value based on the respective time values for each motor sensor measurement; generating a first gain value, a second gain value, and a third gain value, the first gain value being generated based on at least the average time value; and estimating a motor velocity based on at least one motor sensor measurement, the average time value, the first gain value, the second gain value, the third gain value, and at least one previously estimated motor velocity.

Abstract: Embodiments include two-dimensional (2D) semiconductor sheet transistors and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of 2D semiconductor sheets, where individual ones of the 2D semiconductor sheets have a first end and a second end opposite from the first end. In an embodiment, a first spacer is over the first end of the 2D semiconductor sheets, and a second spacer is over the second end of the 2D semiconductor sheets. Embodiments further comprise a gate electrode between the first spacer and the second spacer, a source contact adjacent to the first end of the 2D semiconductor sheets, and a drain contact adjacent to the second end of the 2D semiconductor sheets.