Patents by Inventor Ashish Verma Penumatcha

Ashish Verma Penumatcha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210167182
    Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Seung Hoon SUNG, Ashish Verma PENUMATCHA, Sou-Chi CHANG, Devin MERRILL, I-Cheng TUNG, Nazila HARATIPOUR, Jack T. KAVALIEROS, Ian A. YOUNG, Matthew V. METZ, Uygar E. AVCI, Chia-Ching LIN, Owen LOH, Shriram SHIVARAMAN, Eric Charles MATTSON
  • Publication number: 20210167073
    Abstract: A device is disclosed. The device includes a substrate that includes a base portion and a fin portion that extends upward from the base portion, an insulator layer on sides and top of the fin portion, a first conductor layer on a first side surface of the insulator layer, a second conductor layer on a second side surface of the insulator layer, and a ferroelectric layer on portions of a top surface of the base portion, a portion of the insulator layer below the first conductor layer, a side and top surface of the first conductor layer, a top surface of the insulator layer above the fin portion, a side and top surface of the second conductor layer, and a portion of the insulator layer below the second conductor layer. A word line conductor is on the top surface of the ferroelectric layer.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Shriram Shivaraman, Seung Hoon Sung, Ashish Verma Penumatcha, Uygar E. Avci
  • Publication number: 20210111179
    Abstract: A memory device comprises a bitline along a first direction. A wordline is along a second direction orthogonal to the first direction. An access transistor is coupled to the bitline and the wordline. A first ferroelectric capacitor is vertically aligned with and coupled to the access transistor. A second ferroelectric capacitor is vertically aligned with the first ferroelectric capacitor and coupled to the access transistor, wherein both the first ferroelectric capacitor and the second ferroelectric capacitor are controlled by the access transistor.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 15, 2021
    Inventors: Shriram SHIVARAMAN, Sou-Chi CHANG, Ashish Verma PENUMATCHA, Nazila HARATIPOUR, Uygar E. AVCI
  • Patent number: 10886265
    Abstract: An embodiment includes an apparatus comprising: a dielectric material including fixed charges, the fixed charges each having a first polarity; a channel comprising a channel material, the channel material including a 2-dimensional (2D) material; a drain node; and a source node including a source material, the source material including at least one of the 2D material and an additional 2D material; wherein the source material: (a) includes charges each having a second polarity that is opposite the first polarity, (b) directly contacts the dielectric material. Other embodiments are described herein.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Patent number: 10886286
    Abstract: An embodiment includes a substrate having a surface; a first layer that includes a metal and is on the substrate; a second layer that includes the metal and is on the first layer; a first switching device between the first and second layers; a second switching device between the first and second layers; a capacitor between the first and second layers, the capacitor including ferroelectric materials; a memory cell that includes the first switching device and the capacitor; an interconnect line that couples the first and second switching devices to each other; wherein: (a) the surface is substantially disposed in a first plane, and (b) a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices. Other embodiments are addressed herein.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Ashish Verma Penumatcha, Daniel H. Morris, Uygar E. Avci, Ian A. Young
  • Publication number: 20200403081
    Abstract: Described is a transistor which includes: a source region; a drain region; and a gate region between the source and drain regions, wherein the gate region comprises: high-K dielectric material between spacers such that the high-K dielectric material is recessed; and metal electrode on the recessed high-K dielectric material. The gate recessed gate dielectric allows for using thick gate dielectric even with much advanced process technology nodes (e.g., 7 nm and below).
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Inventors: Seung Hoon Sung, Sou-Chi Chang, Ashish Verma Penumatcha, Nazila Haratipour, Matthew Metz, Michael Harper, Jack Kavalieros, Uygar Avci, Ian Young
  • Publication number: 20200312950
    Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Nazila HARATIPOUR, Chia-Ching LIN, Sou-Chi CHANG, Ashish Verma PENUMATCHA, Owen LOH, Mengcheng LU, Seung Hoon SUNG, Ian A. YOUNG, Uygar AVCI, Jack T. KAVALIEROS
  • Publication number: 20200312978
    Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Jack KAVALIEROS, Ian YOUNG, Matthew METZ, Uygar AVCI, Chia-Ching LIN, Owen LOH, Seung Hoon SUNG, Aditya KASUKURTI, Sou-Chi CHANG, Tanay GOSAVI, Ashish Verma PENUMATCHA
  • Publication number: 20200312976
    Abstract: Techniques and mechanisms to provide electrical insulation between a gate and a channel region of a non-planar circuit device. In an embodiment, the gate structure, and insulation spacers at opposite respective sides of the gate structure, each extend over a semiconductor fin structure. In a region between the insulation spacers, a first dielectric layer extends conformally over the fin, and a second dielectric layer adjoins and extends conformally over the first dielectric layer. A third dielectric layer, adjoining the second dielectric layer and the insulation spacers, extends under the gate structure. Of the first, second and third dielectric layers, the third dielectric layer is conformal to respective sidewalls of the insulation spacers. In another embodiment, the second dielectric layer is of dielectric constant which is greater than that of the first dielectric layer, and equal to or less than that of the third dielectric layer.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Seung Hoon Sung, Jack Kavalieros, Ian Young, Matthew Metz, Uygar Avci, Devin Merrill, Ashish Verma Penumatcha, Chia-Ching Lin, Owen Loh
  • Publication number: 20200312949
    Abstract: A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Nazila HARATIPOUR, Chia-Ching LIN, Sou-Chi CHANG, Ashish Verma PENUMATCHA, Owen LOH, Mengcheng LU, Seung Hoon SUNG, Ian A. YOUNG, Uygar AVCI, Jack T. KAVALIEROS
  • Publication number: 20200286984
    Abstract: Disclosed herein are capacitors with ferroelectric or antiferroelectric (FE/AFE) material and dielectric material, as well as related methods and devices. In some embodiments, a capacitor may include two electrodes, a layer of FE/AFE material between the electrodes, and a layer of dielectric material between the electrodes.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Sou-Chi Chang, Chia-Ching Lin, Ashish Verma Penumatcha, Uygar E. Avci, Ian A. Young
  • Publication number: 20200286686
    Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sou-Chi Chang, Ashish Verma Penumatcha, Nazila Haratipour, Seung Hoon Sung, Owen Y. Loh, Jack Kavalieros, Uygar E. Avci, Ian A. Young
  • Publication number: 20200286685
    Abstract: Described is a ferroelectric based capacitor that reduces non-polar monoclinic phase and increases polar orthorhombic phase by epitaxial strain engineering in the oxide thin film and/or electrodes. As such, both memory window and reliability are improved. The capacitor comprises: a first structure comprising metal, wherein the first structure has a first lattice constant; a second structure comprising metal, wherein the second structure has a second lattice constant; and a third structure comprising ferroelectric material (e.g., oxide of Hf or Zr), wherein the third structure is between and adjacent to the first and second structures, wherein the third structure has a third lattice constant, and wherein the first and second lattice constants are smaller than the third lattice constant.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sou-Chi Chang, Ashish Verma Penumatcha, Nazila Haratipour, Seung Hoon Sung, Owen Y. Loh, Jack Kavalieros, Uygar E. Avci, Ian A. Young
  • Publication number: 20200287017
    Abstract: A gate stack is described that uses anti-ferroelectric material (e.g., Si, La, N, Al, Zr, Ge, Y doped HfO2) or ferroelectric material (e.g., Si, La, N, Al, Zr, Ge, Y doped HfO2, perovskite ferroelectric such as NH4H2PO4, KH2PO4, LiNb03, LiTaO3, BaTiO3, PbTiO3, Pb (Zr,Ti) O3, (Pb,La)TiO3, and (Pb,La)(Zr,Ti)O3) which reduces write voltage, improves endurance, and increases retention. The gate stack of comprises strained anti-FE or FE material and depolarized anti-FE or FE. The endurance of the FE transistor is further improved by using a higher K (constant) dielectric (e.g., SiO2, Al2O3, HfO2, Ta2O3, La2O3) in the gate stack. High K effects may also be achieved by depolarizing the FE or FE oxide in the transistor gate stack.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Sou-Chi CHANG, Chia-Chang LIN, Seung Hoon SUNG, Ashish Verma PENUMATCHA, Nazila HARATIPOURA, Owen LOH, Jack KAVALIEROS, Uygar AVCI, Ian YOUNG
  • Publication number: 20200286687
    Abstract: Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sou-Chi Chang, Nazila Haratipour, Seung Hoon Sung, Ashish Verma Penumatcha, Jack Kavalieros, Uygar E. Avci, Ian A. Young
  • Publication number: 20200212224
    Abstract: Embodiments herein describe techniques for a semiconductor device including a gate stack with a ferroelectric-oxide layer above a channel layer and in contact with the channel layer, and a top electrode above the ferroelectric-oxide layer. The ferroelectric-oxide layer includes a domain wall between an area under a nucleation point of the top electrode and above a separation line of the channel layer between an ON state portion and an OFF state portion of the channel layer. A resistance between a source electrode and a drain electrode is modulated in a range between a first resistance value and a second resistance value, dependent on a position of the domain wall within the ferroelectric-oxide layer, a position of the ON state portion of the channel layer, and a position of the OFF state portion of the channel layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 26, 2018
    Publication date: July 2, 2020
    Inventors: Ashish Verma PENUMATCHA, Tanay GOSAVI, Uygar AVCI, Ian A. YOUNG
  • Publication number: 20200212193
    Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation Santa Clara
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Publication number: 20200212532
    Abstract: Describe is a resonator that uses ferroelectric (FE) material in a capacitive structure. The resonator includes a first plurality of metal lines extending in a first direction; an array of capacitors comprising ferroelectric material; a second plurality of metal lines extending in the first direction, wherein the array of capacitors is coupled between the first and second plurality of metal lines; and a circuitry to switch polarization of at least one capacitor of the array of capacitors. The switching of polarization regenerates acoustic waves. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using metal lines above and adjacent to the FE based capacitors.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Publication number: 20200212194
    Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Publication number: 20200105774
    Abstract: An embodiment includes a substrate having a surface; a first layer that includes a metal and is on the substrate; a second layer that includes the metal and is on the first layer; a first switching device between the first and second layers; a second switching device between the first and second layers; a capacitor between the first and second layers, the capacitor including ferroelectric materials; a memory cell that includes the first switching device and the capacitor; an interconnect line that couples the first and second switching devices to each other; wherein: (a) the surface is substantially disposed in a first plane, and (b) a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices. Other embodiments are addressed herein.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Ashish Verma Penumatcha, Daniel H. Morris, Uygar E. Avci, Ian A. Young