Patents by Inventor Ashish Verma

Ashish Verma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200286686
    Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sou-Chi Chang, Ashish Verma Penumatcha, Nazila Haratipour, Seung Hoon Sung, Owen Y. Loh, Jack Kavalieros, Uygar E. Avci, Ian A. Young
  • Publication number: 20200286685
    Abstract: Described is a ferroelectric based capacitor that reduces non-polar monoclinic phase and increases polar orthorhombic phase by epitaxial strain engineering in the oxide thin film and/or electrodes. As such, both memory window and reliability are improved. The capacitor comprises: a first structure comprising metal, wherein the first structure has a first lattice constant; a second structure comprising metal, wherein the second structure has a second lattice constant; and a third structure comprising ferroelectric material (e.g., oxide of Hf or Zr), wherein the third structure is between and adjacent to the first and second structures, wherein the third structure has a third lattice constant, and wherein the first and second lattice constants are smaller than the third lattice constant.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sou-Chi Chang, Ashish Verma Penumatcha, Nazila Haratipour, Seung Hoon Sung, Owen Y. Loh, Jack Kavalieros, Uygar E. Avci, Ian A. Young
  • Publication number: 20200286984
    Abstract: Disclosed herein are capacitors with ferroelectric or antiferroelectric (FE/AFE) material and dielectric material, as well as related methods and devices. In some embodiments, a capacitor may include two electrodes, a layer of FE/AFE material between the electrodes, and a layer of dielectric material between the electrodes.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Sou-Chi Chang, Chia-Ching Lin, Ashish Verma Penumatcha, Uygar E. Avci, Ian A. Young
  • Publication number: 20200287017
    Abstract: A gate stack is described that uses anti-ferroelectric material (e.g., Si, La, N, Al, Zr, Ge, Y doped HfO2) or ferroelectric material (e.g., Si, La, N, Al, Zr, Ge, Y doped HfO2, perovskite ferroelectric such as NH4H2PO4, KH2PO4, LiNb03, LiTaO3, BaTiO3, PbTiO3, Pb (Zr,Ti) O3, (Pb,La)TiO3, and (Pb,La)(Zr,Ti)O3) which reduces write voltage, improves endurance, and increases retention. The gate stack of comprises strained anti-FE or FE material and depolarized anti-FE or FE. The endurance of the FE transistor is further improved by using a higher K (constant) dielectric (e.g., SiO2, Al2O3, HfO2, Ta2O3, La2O3) in the gate stack. High K effects may also be achieved by depolarizing the FE or FE oxide in the transistor gate stack.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Sou-Chi CHANG, Chia-Chang LIN, Seung Hoon SUNG, Ashish Verma PENUMATCHA, Nazila HARATIPOURA, Owen LOH, Jack KAVALIEROS, Uygar AVCI, Ian YOUNG
  • Publication number: 20200212193
    Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation Santa Clara
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Publication number: 20200212532
    Abstract: Describe is a resonator that uses ferroelectric (FE) material in a capacitive structure. The resonator includes a first plurality of metal lines extending in a first direction; an array of capacitors comprising ferroelectric material; a second plurality of metal lines extending in the first direction, wherein the array of capacitors is coupled between the first and second plurality of metal lines; and a circuitry to switch polarization of at least one capacitor of the array of capacitors. The switching of polarization regenerates acoustic waves. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using metal lines above and adjacent to the FE based capacitors.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Publication number: 20200211708
    Abstract: A method is disclosed for monitoring or delaying or preventing or combinations thereof, the onset of Type 2 diabetes or reducing blood sugar level to a normal range that includes interfacing, via a computer-based system, a user device with a processor in communication with one or more data bases; inputting at least one user profile into one or more of the data bases; inputting data into one or more data bases wherein the data relates to diabetes optimized dietetic or diabetes optimized exercise or weight or combinations for at least one user corresponding to the at least one user profile; and presenting to at least one user a summary of the data input into the one or more data bases wherein the data relates to diabetes optimized dietetic or diabetes optimized exercise or weight or combinations. A corresponding system and an article of manufacturing are also disclosed.
    Type: Application
    Filed: February 18, 2020
    Publication date: July 2, 2020
    Inventors: Christine Tinio Geronimo-Button, Terry Michael Button, Ashish Verma
  • Publication number: 20200212194
    Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Publication number: 20200212224
    Abstract: Embodiments herein describe techniques for a semiconductor device including a gate stack with a ferroelectric-oxide layer above a channel layer and in contact with the channel layer, and a top electrode above the ferroelectric-oxide layer. The ferroelectric-oxide layer includes a domain wall between an area under a nucleation point of the top electrode and above a separation line of the channel layer between an ON state portion and an OFF state portion of the channel layer. A resistance between a source electrode and a drain electrode is modulated in a range between a first resistance value and a second resistance value, dependent on a position of the domain wall within the ferroelectric-oxide layer, a position of the ON state portion of the channel layer, and a position of the OFF state portion of the channel layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 26, 2018
    Publication date: July 2, 2020
    Inventors: Ashish Verma PENUMATCHA, Tanay GOSAVI, Uygar AVCI, Ian A. YOUNG
  • Publication number: 20200183499
    Abstract: A Head Mounted Display (HMD) device includes a display configured to display an augmented reality effect in relation to an Electromyography (EMG) device. The HMD device also includes at least one processor configured to control the display of the augmented reality effect in relation to the EMG device according to a user motion detected by the EMG device. The HMD device may further include a communication unit configured to communicate with the EMG device, and the at least one processor may be configured to receive, from the EMG device via the communication unit, information about data stored on the EMG device. At least some of the received information may be displayed in relation to the EMG device as the augmented reality effect. Information sent from the EMG device to a mobile terminal may be displayed in relation to the EMG device as the augmented reality effect.
    Type: Application
    Filed: February 10, 2020
    Publication date: June 11, 2020
    Inventors: William Stryker Clausen, Ashish Verma
  • Publication number: 20200143287
    Abstract: A computer generates labels for machine learning algorithms by retrieving, from a data storage circuit, multiple label sets that contain labels that each classify data points in a corpus of data. A graph is generated that includes a plurality of edges, each edge between two respective labels from different label sets of the multiple label sets. Weights are determined for the plurality of edges based upon a consistency between data points classified by two labels connected by the edges. An algorithm is applied that groups labels from the multiple label sets based upon the weights for the plurality of edges. Data points are identified from the corpus of data that represent conflicts within the grouped labels. An electronic message is transmitted in order to present the identified data points to entities for further classification. A new label set is generated using the further classification received from the entities.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Inventors: Prasanta Ghosh, Shantanu R. Godbole, Sachindra Joshi, Srujana Merugu, Ashish Verma
  • Publication number: 20200125926
    Abstract: Methods, systems, and computer program products for dynamic batch sizing for inferencing of deep neural networks in resource-constrained environments are provided herein. A computer-implemented method includes obtaining, as input for inferencing of one or more deep neural networks, (i) an inferencing model and (ii) one or more resource constraints; computing, based at least in part on the obtained input, a set of statistics pertaining to resource utilization for each of multiple layers in the one or more deep neural networks; determining, based at least in part on (i) the obtained input and (ii) the computed set of statistics, multiple batch sizes to be used for inferencing the multiple layers of the one or more deep neural networks; and outputting, to at least one user, the determined batch sizes to be used for inferencing the multiple layers of the one or more deep neural networks.
    Type: Application
    Filed: October 23, 2018
    Publication date: April 23, 2020
    Inventors: Anamitra Roy Choudhury, Saurabh Goyal, Yogish Sabharwal, Ashish Verma, Dharma Teja Vooturi
  • Patent number: 10628538
    Abstract: Methods, systems, and computer program products for suggesting sensor placements are provided herein.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Saurav Basu, Thomas George, Rashmi Mittal, Chandrasekar Radhakrishnan, Yogish Sabharwal, Ashish Verma
  • Patent number: 10614100
    Abstract: A method comprising using at least one hardware processor for: receiving a topic under consideration (TUC) and a set of claims referring to the TUC; identifying semantic similarity relations between claims of the set of claims; clustering the claims into a plurality of claim clusters based on the identified semantic similarity relations, wherein said claim clusters represent semantically different claims of the set of claims; and generating a list of non-redundant claims comprising said semantically different claims.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mitesh Khapra, Vikas Raykar, Amrita Saha, Noam Slonim, Ashish Verma
  • Publication number: 20200105774
    Abstract: An embodiment includes a substrate having a surface; a first layer that includes a metal and is on the substrate; a second layer that includes the metal and is on the first layer; a first switching device between the first and second layers; a second switching device between the first and second layers; a capacitor between the first and second layers, the capacitor including ferroelectric materials; a memory cell that includes the first switching device and the capacitor; an interconnect line that couples the first and second switching devices to each other; wherein: (a) the surface is substantially disposed in a first plane, and (b) a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices. Other embodiments are addressed herein.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Ashish Verma Penumatcha, Daniel H. Morris, Uygar E. Avci, Ian A. Young
  • Patent number: 10585484
    Abstract: An apparatus, a system, and a method for transferring data from a terminal to an Electromyography (EMG) device are provided. The method includes detecting a user motion, determining whether the user motion corresponds to a motion associated with requesting data to be transferred from the source terminal to the EMG device, and if the user motion corresponds to a motion associated with requesting data to be transferred to from the source terminal to the EMG device, transmitting to the source terminal a request for the data according to the user motion.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: March 10, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: William Stryker Clausen, Ashish Verma
  • Patent number: 10565526
    Abstract: A computer generates labels for machine learning algorithms by retrieving, from a data storage circuit, multiple label sets that contain labels that each classify data points in a corpus of data. A graph is generated that includes a plurality of edges, each edge between two respective labels from different label sets of the multiple label sets. Weights are determined for the plurality of edges based upon a consistency between data points classified by two labels connected by the edges. An algorithm is applied that groups labels from the multiple label sets based upon the weights for the plurality of edges. Data points are identified from the corpus of data that represent conflicts within the grouped labels. An electronic message is transmitted in order to present the identified data points to entities for further classification. A new label set is generated using the further classification received from the entities.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Prasanta Ghosh, Shantanu R. Godbole, Sachindra Joshi, Srujana Merugu, Ashish Verma
  • Publication number: 20190378834
    Abstract: An embodiment includes an apparatus comprising: a dielectric material including fixed charges, the fixed charges each having a first polarity; a channel comprising a channel material, the channel material including a 2-dimensional (2D) material; a drain node; and a source node including a source material, the source material including at least one of the 2D material and an additional 2D material; wherein the source material: (a) includes charges each having a second polarity that is opposite the first polarity, (b) directly contacts the dielectric material. Other embodiments are described herein.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 12, 2019
    Inventors: Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Publication number: 20190267117
    Abstract: In an embodiment, the present invention provides a computer system for use by caregivers in the prevention and treatment of acute otitis media (AOM) with the use of the Galbreath technique in children from shortly after birth to about six years of age. The computer system assists caregivers in the monitoring of children who may be at risk for AOM or who may be experiencing an active episode of AOM. The system may make automated suggestions in real time of treatment options available to a caregiver at home. The computer system may include a diary component, and may include a Virtual Coach component providing reminders in real time and educational materials in the use of the Galbreath Technique and other medical interventions in the prevention and treatment of AOM.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Inventors: Christine Tinio Geronimo-Button, Terry Michael Button, Ashish Verma
  • Publication number: 20190220470
    Abstract: A method and system. Target clusterability is calculated as an average of a respective clusterability of at least one target data item comprised by a target domain. Target-side matchability is calculated as an average of a respective matchability of each target centroid of the target domain to source centroids of a source domain, wherein the source domain comprises at least one source data item. Source-side matchability is calculated as an average of a respective matchability of each source centroid of said source centroids to the target centroids. Source-target pair matchability is calculated as an average of the target-side matchability and the source-side matchability. Cross-domain clusterability between the target domain and the source domain is calculated as a linear combination of the calculated target clusterability and the calculated source-target pair matchability. The cross-domain clusterability is transferred to a device.
    Type: Application
    Filed: March 25, 2019
    Publication date: July 18, 2019
    Inventors: JEFFREY M. ACHTERMANN, INDRAJIT BHATTACHARYA, KEVIN W. ENGLISH, SHANTANU R. GODBOLE, SACHINDRA JOSHI, ASHWIN SRINIVASAN, ASHISH VERMA