Abstract: One embodiment provides a method, including: receiving at least one deep learning job for scheduling and running on a distributed system comprising a plurality of nodes; receiving a batch size range indicating a minimum batch size and a maximum batch size that can be utilized for running the at least one deep learning job; determining a plurality of runtime estimations for running the at least one deep learning job; creating a list of optimal combinations of (i) batch sizes and (ii) numbers of the plurality of nodes for running both (a) the at least one deep learning job and (b) current deep learning jobs; and scheduling the at least one deep-learning job at the distributed system, responsive to identifying, by utilizing the list, that the distributed system has necessary processing resources for running both (iii) the at least one deep learning job and (iv) the current deep learning jobs.

Abstract: Systems, computer-implemented methods, and computer program products that can facilitate switching a model training process from a ground truth training phase to an adversarial training phase based on performance of a model trained in the ground truth training phase are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an analysis component that identifies a performance condition of a model trained in a model training process. The computer executable components can further comprise a trainer component that switches the model training process from a ground truth training process to an adversarial training process based on the identified performance condition.

Abstract: Techniques regarding determining hyperparameters for a differentially private federated learning process are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a hyperparameter advisor component that determines a hyperparameter for a model of a differentially private federated learning process based on a defined numeric relationship between a privacy budget, a learning rate schedule, and a batch size.

Abstract: Methods, systems, and computer program products for determining operating range of hyperparameters are provided herein. A computer-implemented method includes obtaining a machine learning model, a list of candidate values for a hyperparameter, and a dataset; performing one or more hyperparameter range trials based on the machine learning model, the list of candidate values for the hyperparameter, and the dataset; automatically determining an operating range of the hyperparameter based on the one or more hyperparameter range trials; and training the machine learning model to convergence based at least in part on the determined operating range.

Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack.

Abstract: A device is disclosed. The device includes a substrate that includes a base portion and a fin portion that extends upward from the base portion, an insulator layer on sides and top of the fin portion, a first conductor layer on a first side surface of the insulator layer, a second conductor layer on a second side surface of the insulator layer, and a ferroelectric layer on portions of a top surface of the base portion, a portion of the insulator layer below the first conductor layer, a side and top surface of the first conductor layer, a top surface of the insulator layer above the fin portion, a side and top surface of the second conductor layer, and a portion of the insulator layer below the second conductor layer. A word line conductor is on the top surface of the ferroelectric layer.

Abstract: Embodiments relate to training a machine learning model based on an iterative algorithm in a distributed, federated, private, and secure manner. Participating entities are registered in a collaborative relationship. The registered participating entities are arranged in a topology and a topological communication direction is established. Each registered participating entity receives a public additive homomorphic encryption (AHE) key and local machine learning model weights are encrypted with the received public key. The encrypted local machine learning model weights are selectively aggregated and distributed to one or more participating entities in the topology responsive to the topological communication direction. The aggregated sum of the encrypted local machine learning model weights is subjected to decryption with a corresponding private AHE key. The decrypted aggregated sum of the encrypted local machine learning model weights is shared with the registered participating entities.

Abstract: A memory device comprises a bitline along a first direction. A wordline is along a second direction orthogonal to the first direction. An access transistor is coupled to the bitline and the wordline. A first ferroelectric capacitor is vertically aligned with and coupled to the access transistor. A second ferroelectric capacitor is vertically aligned with the first ferroelectric capacitor and coupled to the access transistor, wherein both the first ferroelectric capacitor and the second ferroelectric capacitor are controlled by the access transistor.

Abstract: Methods, systems, and computer program products for determining optimal compute resources for distributed batch based optimization applications are provided herein. A method includes obtaining a size of an input dataset, a size of a model, and a set of batch sizes corresponding to a job to be processed using a distributed computing system; computing, based at least in part on the set of batch sizes, one or more node counts corresponding to a number of nodes that can be used for processing said job; estimating, for each given one of the node counts, an execution time to process the job based on an average computation time for a batch of said input dataset and an average communication time for said batch of said input dataset; and selecting, based at least in part on said estimating, at least one of said node counts for processing the job.

Abstract: A computer generates labels for machine learning algorithms by retrieving, from a data storage circuit, multiple label sets that contain labels that each classify data points in a corpus of data. A graph is generated that includes a plurality of edges, each edge between two respective labels from different label sets of the multiple label sets. Weights are determined for the plurality of edges based upon a consistency between data points classified by two labels connected by the edges. An algorithm is applied that groups labels from the multiple label sets based upon the weights for the plurality of edges. Data points are identified from the corpus of data that represent conflicts within the grouped labels. An electronic message is transmitted in order to present the identified data points to entities for further classification. A new label set is generated using the further classification received from the entities.

Abstract: An embodiment includes an apparatus comprising: a dielectric material including fixed charges, the fixed charges each having a first polarity; a channel comprising a channel material, the channel material including a 2-dimensional (2D) material; a drain node; and a source node including a source material, the source material including at least one of the 2D material and an additional 2D material; wherein the source material: (a) includes charges each having a second polarity that is opposite the first polarity, (b) directly contacts the dielectric material. Other embodiments are described herein.

Abstract: An embodiment includes a substrate having a surface; a first layer that includes a metal and is on the substrate; a second layer that includes the metal and is on the first layer; a first switching device between the first and second layers; a second switching device between the first and second layers; a capacitor between the first and second layers, the capacitor including ferroelectric materials; a memory cell that includes the first switching device and the capacitor; an interconnect line that couples the first and second switching devices to each other; wherein: (a) the surface is substantially disposed in a first plane, and (b) a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices. Other embodiments are addressed herein.

Abstract: Methods, systems, and computer program products for dataset dependent low rank decomposition of neural networks are provided herein. A computer-implemented method includes obtaining a target dataset and a trained model of a neural network; providing at least a portion of the target dataset to the trained model; determining relevance of each of one or more of filters of the neural network and channels of the neural network to the target dataset based on the provided portion, wherein the one or more of the filters and the channels correspond to at least one layer of the neural network; and compressing the trained model of the neural network based at least in part on the determined relevancies.

Abstract: Described is a transistor which includes: a source region; a drain region; and a gate region between the source and drain regions, wherein the gate region comprises: high-K dielectric material between spacers such that the high-K dielectric material is recessed; and metal electrode on the recessed high-K dielectric material. The gate recessed gate dielectric allows for using thick gate dielectric even with much advanced process technology nodes (e.g., 7 nm and below).

Abstract: Methods, systems, and computer program products for determining intermittent renewable energy penetration limits in a grid are provided herein.

Abstract: A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.

Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.

Abstract: Techniques and mechanisms to provide electrical insulation between a gate and a channel region of a non-planar circuit device. In an embodiment, the gate structure, and insulation spacers at opposite respective sides of the gate structure, each extend over a semiconductor fin structure. In a region between the insulation spacers, a first dielectric layer extends conformally over the fin, and a second dielectric layer adjoins and extends conformally over the first dielectric layer. A third dielectric layer, adjoining the second dielectric layer and the insulation spacers, extends under the gate structure. Of the first, second and third dielectric layers, the third dielectric layer is conformal to respective sidewalls of the insulation spacers. In another embodiment, the second dielectric layer is of dielectric constant which is greater than that of the first dielectric layer, and equal to or less than that of the third dielectric layer.

Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

Abstract: Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.