Patents by Inventor Ashish .

Ashish . has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200318605
    Abstract: Provided is a wind turbine blade for a wind turbine, the wind turbine blade including a root, a tip, a trailing edge, a leading edge and at least two beams including carbon fiber-reinforced plastic and being spaced apart from one another, wherein the at least two beams are arranged in the wind turbine blade in the longitudinal direction of the wind turbine blade at the trailing edge or within a distance of 25% of the width from the trailing edge, whereby the at least two beams are electrically connected to one another by at least one electrically conductive member and at least one of the at least two beams and/or at least one of the at least one electrically conductive member is configured to be connected to a down conductor of the wind turbine.
    Type: Application
    Filed: March 30, 2020
    Publication date: October 8, 2020
    Inventors: Claus Burchardt, Soeren Randrup Daugaard Henrichsen, Ashish Pawar
  • Publication number: 20200320847
    Abstract: A system and computer-implemented method for efficiently monitoring hand hygiene is provided. The system comprises one or more sensors configured to determine presence of one or more individuals in vicinity. The system further comprises one or more controllers configured to ascertain identity of the one or more individuals. The one or more controllers are further configured to send one or more alerts to the one or more identified individuals to wash their hands. Furthermore, the one or more controllers are configured to monitor one or more handwashing instances by the one or more identified individuals and generate one or more compliance results for each of the one or more monitored handwashing instances. The one or more controllers are also configured to initiate one or more actions corresponding to each of the one or more monitored handwashing instances based on the generated one or more compliance results.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Nitesh Dattu Waghode, Vivek Vasant Diwanji, Amit Bindumadhav Pingle, Himanshu Pradhan, Mandar Pandurang Patil, Aman Singhal, Ashish Sharma
  • Publication number: 20200320489
    Abstract: Embodiments provide methods, and systems for facilitating microservices for cryptographic operations. A method includes receiving, by a server system, a cryptographic service request from at least one application of a plurality of applications over a network communication channel. The cryptographic service request comprises a cryptographic operation to be performed and a cryptographic keys index being an identifier of the at least one application. The method includes generating, by the server system, a cryptographic operation command for the cryptographic operation. The method includes sending, by the server system, the cryptographic operation command to a Hardware Security Module (HSM) communicatively connected to the server system to perform the cryptographic operation. The method includes receiving, by the server system, a response from the HSM for the performed cryptographic operation.
    Type: Application
    Filed: April 7, 2020
    Publication date: October 8, 2020
    Applicant: Mastercard International Incorporated
    Inventors: Sunil Vagare, Chetan Bhalerao, Ritesh Chaudhari, Sudhir Shirke, Ashish Dhande
  • Publication number: 20200317560
    Abstract: The present disclosure describes spill retention mechanisms for cooktops and other substrates. The spill retention mechanisms can hinder the movement of liquids primarily due to the physical attributes of the mechanisms, unlike hydrophobic mechanisms which hinder movement primarily due to the chemical attributes of the hydrophobic material.
    Type: Application
    Filed: March 31, 2020
    Publication date: October 8, 2020
    Applicants: SCHOTT AG, SCHOTT Corporation
    Inventors: Ashish Lepcha, Angelina Milanovska, Cynthia Decker, Zachary D Wimmer, Martin Müller, Silke Knoche
  • Patent number: 10798530
    Abstract: Schemes, methods and examples for optimization of broadcast and multicast frame delivery when at least one client device in a basic service set (BSS) is in a power-save mode are described. A communication apparatus associated with a BSS receives a broadcast or multicast frame after a first Delivery Traffic Indication Map (DTIM). The communication apparatus transmits the broadcast or multicast frame to at least a first client device in the BSS, without buffering the broadcast or multicast frame for transmission following a second DTIM which is subsequent the first DTIM, while at least a second client device in the BSS is in a power-save mode.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: October 6, 2020
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Joyjit Mullick, Ashish Kumar, Saurabh Agarwal, Abhishek Chaudhary, Abhijit Uplenchwar
  • Patent number: 10792462
    Abstract: A context-sensitive soundscape is generated by receiving a first identifier for identifying a target cognitive state for a user, and a second identifier for identifying a user cohort for the user. A present context is determined for the user. A machine-learning procedure is performed to map the target cognitive state to a set of audio output characteristics based upon the identified user cohort and the determined present context. An audio output is generated to create the context-sensitive soundscape that includes the set of audio output characteristics.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Gordon, James R. Kozloski, Ashish Kundu, Clifford A. Pickover
  • Patent number: 10796081
    Abstract: Electronic form (e-form) processing includes generating an e-form based on a form template, the form template being selected from pre-defined form templates. The e-form includes modular sections arranged in a pre-defined order, each modular section being associated with user privileges. Further, data is retrieved from at least one database to partly populate at least one of the modular sections in the e-form. Subsets of the modular sections are provided to designated users based on the user privileges and a workflow associated with the e-form. A processed e-form, including the retrieved data and the data inputs, and having at least one external document, is created based on data inputs received from the designated users. A processed electronic document including the modular sections populated with the retrieved data, the data inputs, and external data from the external document arranged in the pre-defined order is generated from the processed e-form.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: October 6, 2020
    Assignee: Tata Consultancy Services Limited
    Inventors: Tripat Singh Kharbanda, Sarabdeep Singh, Gaurav Kandpal, Kunal Kumar, Ashish Kumar Gupta, Anupam Grover, Vidhi Lohani
  • Patent number: 10795705
    Abstract: A data parallel pipeline may specify multiple parallel data objects that contain multiple elements and multiple parallel operations that operate on the parallel data objects. Based on the data parallel pipeline, a dataflow graph of deferred parallel data objects and deferred parallel operations corresponding to the data parallel pipeline may be generated and one or more graph transformations may be applied to the dataflow graph to generate a revised dataflow graph that includes one or more of the deferred parallel data objects and deferred, combined parallel data operations. The deferred, combined parallel operations may be executed to produce materialized parallel data objects corresponding to the deferred parallel data objects.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: October 6, 2020
    Assignee: Google LLC
    Inventors: Craig D. Chambers, Ashish Raniwala, Frances J. Perry, Stephen R. Adams, Robert R. Henry, Robert Bradshaw, Nathan Weizenbaum
  • Patent number: 10795652
    Abstract: Disclosed herein are representative embodiments of tools and techniques for installing, executing, and/or updating managed applications through generation of native code from code in an intermediate language. According to one exemplary technique, a computing device receives machine dependent intermediate language code (MDIL code) generated by an online provider for an application. Additionally, the computing device installs the application on the computing device by generating a native image for the application, which includes binding a portion of the MDIL code with one or more libraries on the computing device. Also, the native image is stored on the computing device for use in loading the application for execution.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 6, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sameer Tejani, Adina Magdalena Trufinescu, Yasser Shaaban, Abolade Gbadegesin, Ashish Babbar, Mei-Chin Tsai, Subramanian Ramaswamy, Casimir Lakshan Fernando
  • Publication number: 20200311728
    Abstract: A method of verifying the destination of a transaction between nodes in a network includes receiving transaction information corresponding to a transaction between the nodes, where the transaction information comprises a unique destination identifier and a destination name and where the unique destination identifier defines a destination account of the transaction; obtaining from a storage unit a set of names used in previous transactions to that destination account; determining at least one disparity value between the destination name and the set of names; and producing a destination verification value based on the at least one disparity value, wherein the destination verification value is used to verify whether the transaction between nodes should proceed.
    Type: Application
    Filed: March 20, 2020
    Publication date: October 1, 2020
    Inventors: Ashish Jain, Bhupinder Singh Narang, Pulkit Gupta, Michael Alan Dewar, Jeremy Robert Stephens
  • Publication number: 20200312971
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a FinFET transistor on the substrate. The FinFET transistor includes a fin structure having a channel area, a source area, and a drain area. The FinFET transistor further includes a gate dielectric area between spacers above the channel area of the fin structure and below a top surface of the spacers; spacers above the fin structure and around the gate dielectric area; and a metal gate conformally covering and in direct contact with sidewalls of the spacers. The gate dielectric area has a curved surface. The metal gate is in direct contact with the curved surface of the gate dielectric area. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Ashish PENUMATCHA, Seung Hoon SUNG, Scott CLENDENNING, Uygar AVCI, Ian A. YOUNG, Jack T. KAVALIEROS
  • Publication number: 20200308030
    Abstract: The invention provides a process for treating waste water from an industrial process for producing propylene oxide, which comprises subjecting the waste water to a catalytic wet oxidation treatment comprising: feeding a stream comprising the waste water to a reactor; subjecting the stream comprising the waste water to an oxidation treatment in the presence of oxygen and a catalyst resulting in a treated stream; sending at least part of the treated stream to a separator wherein the treated stream is separated into a gas stream and a liquid stream; and recycling part of the liquid stream to the reactor.
    Type: Application
    Filed: November 20, 2018
    Publication date: October 1, 2020
    Inventors: Kaushik BASAK, Arian VAN MOURIK, Nishith VERMA, Ashish YADAV
  • Publication number: 20200312976
    Abstract: Techniques and mechanisms to provide electrical insulation between a gate and a channel region of a non-planar circuit device. In an embodiment, the gate structure, and insulation spacers at opposite respective sides of the gate structure, each extend over a semiconductor fin structure. In a region between the insulation spacers, a first dielectric layer extends conformally over the fin, and a second dielectric layer adjoins and extends conformally over the first dielectric layer. A third dielectric layer, adjoining the second dielectric layer and the insulation spacers, extends under the gate structure. Of the first, second and third dielectric layers, the third dielectric layer is conformal to respective sidewalls of the insulation spacers. In another embodiment, the second dielectric layer is of dielectric constant which is greater than that of the first dielectric layer, and equal to or less than that of the third dielectric layer.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Seung Hoon Sung, Jack Kavalieros, Ian Young, Matthew Metz, Uygar Avci, Devin Merrill, Ashish Verma Penumatcha, Chia-Ching Lin, Owen Loh
  • Publication number: 20200312414
    Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.
    Type: Application
    Filed: June 12, 2020
    Publication date: October 1, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Ashish Baraskar, Ching-Huang Lu, Vinh Diep, Yingda Dong
  • Publication number: 20200311049
    Abstract: There are provided systems and methods for determining data validity during data processing for multiple processing stacks. During processing requests with a service provider, each request may go through a data flow that invokes multiple processing stacks, where the data is transmitted over a network to different data processing nodes. For example, a distributed computing architecture may invoke multiple disparate nodes to process data, which may become corrupted during data transmission and processing. To ensure data validity, a framework may be provided that provided data translators for each processing stack to covert data handled in a processing format for that stack into a base data format utilized by the framework. The framework may utilize checksums or other hash values of the data in the base data format to determine if the data has been altered at different processing nodes or stacks.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Shanmugasundaram Alagumuthu, Vikas Prabhakar, Ashish Srivastava
  • Publication number: 20200312950
    Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Nazila HARATIPOUR, Chia-Ching LIN, Sou-Chi CHANG, Ashish Verma PENUMATCHA, Owen LOH, Mengcheng LU, Seung Hoon SUNG, Ian A. YOUNG, Uygar AVCI, Jack T. KAVALIEROS
  • Publication number: 20200308916
    Abstract: The systems, devices, and methods described herein relate to a double layer racking board on a land-based drilling rig. The double layer racking board may include a drill pipe racking board and a casing racking board. The drill pipe racking board may be positioned at a different height than the casing racking board, such than operator is able to comfortably access drill pipe stands and casing stands of different heights via the racking boards. The double layer racking board may allow for the performance of a first drilling operation involving drill pipe stands at the same time as the performance of a second drilling operation involving casing.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventor: Ashish Gupta
  • Publication number: 20200309848
    Abstract: An integrated circuit (IC) chip for providing a safety-critical value includes first and second processing paths. The first processing path includes a first processing element and is coupled to receive a first input signal on a first input pin and to provide a first output signal that provides the safety-critical value on an output pin. The second processing path includes a second processing element and is coupled to receive a second input signal and to provide a second output signal. The first processing path and the second processing path are independent of each other. A smart comparator on the IC chip receives the first output signal and the second output signal and initiates a remedial action responsive to a difference between the first output signal and the second output signal reaching a configurable threshold.
    Type: Application
    Filed: April 13, 2020
    Publication date: October 1, 2020
    Inventors: Jeffrey Earl Stafford, Prasanth Viswanathan Pillai, Ashish Arvind Vanjari
  • Publication number: 20200313001
    Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Ryan KEECH, Benjamin CHU-KUNG, Subrina RAFIQUE, Devin MERRILL, Ashish AGRAWAL, Harold KENNEL, Yang CAO, Dipanjan BASU, Jessica TORRES, Anand MURTHY
  • Publication number: 20200305613
    Abstract: An escapement mechanism of a cutlery dispenser causes a cutlery article to fall from a vertical stack onto a slide track that guides it to a dispensing position. A slide channel and head channel of the slide track can laterally confine the cutlery article. A dampening surface can reduce cutlery bouncing and skewing. The escapement mechanism can include at least three pivots and/or a coil return spring. Dispensers can be installed in a base in any desired combination and retained therein by compatible features such as flanges and slots that prevent dispenser tipping. In embodiments, individual dispensers can be horizontally slid part-way out of the base to access side features that would otherwise be obscured by a neighboring dispenser. A cutlery quantity indicator can laterally contact the cutlery stack and can pivot to display a low-cutlery signal when the cutlery stack falls below an indicator height.
    Type: Application
    Filed: March 26, 2020
    Publication date: October 1, 2020
    Applicant: Waddington North America, Inc.
    Inventors: Ashish K Mithal, William A Gallop