Patents by Inventor Ashish .

Ashish . has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12099969
    Abstract: An example operation may include one or more of receiving, by a retailer node, an encrypted inventory of goods data from a plurality of supplier nodes over a blockchain network, computing, by the retailer node, an ordering proportion based on the encrypted inventory of goods data, generating, by the retailer node, an ordering policy based on the ordering proportion, and executing a smart contract to order goods from the plurality of the supplier nodes based on the ordering policy.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: September 24, 2024
    Assignee: International Business Machines Corporation
    Inventors: Elisabeth Claire Paulson, Ashish Jagmohan, Ajay Ashok Deshpande, Pavithra Harsha, Ali Koc, Krishna Chaitanya Ratakonda, Ramesh Gopinath
  • Patent number: 12097197
    Abstract: The present invention relates to stable liquid compositions suitable for parenteral administration in the form of a solution comprising: (a) netupitant and optionally palonosetron; (b) at least one pharmaceutically acceptable stabilizer; (c) at least one pharmaceutically acceptable solubilizer; and (d) at least one pharmaceutically acceptable vehicle, wherein netupitant is present at a concentration of about 0.5 mg/mL to about 20 mg/mL and the solution has a pH of about 2 to about 6. The compositions are suitable for subcutaneous, intravenous, or intramuscular administration. The invention further relates to methods for manufacturing the compositions and methods of using such compositions for prevention, treatment or management of nausea and vomiting.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: September 24, 2024
    Assignee: Slayback Pharma LLC
    Inventors: Ashish Anilrao Dubewar, Rahul Dhulaji Bhise, Mahadeo Vasant Mahadik, Shanker Mamidi, Mayur Anshiram Adhav, Raghavender Rao Kategher, Nagaraj Gangam, Sumitra Ashokkumar Pillai, Praveen Kumar Subbappa
  • Patent number: 12099976
    Abstract: A system, method implemented on a computer system, and computer program product for generating an expression. A graphical representation of the expression comprising criteria blocks and logical operator blocks is displayed on a user interface. Each of the criteria blocks includes criteria information defining a criteria, an edit block control element, and a delete block control element. A user interface to receive changes to the criteria information for a selected criteria block is displayed in response to selecting the edit block control element for the selected criteria block. The selected criteria block is deleted from the expression in response to selecting the delete block control element for the selected criteria block. A building block may be used to define criteria for criteria blocks in several expressions. Criteria for expressions defined using a building block are changed automatically in response to changes to the building block.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: September 24, 2024
    Assignee: ADP, Inc.
    Inventors: Kyle Vining, Peter Faria, Ashish Garwal, Pooja Keswani, Carl Pereira
  • Patent number: 12101836
    Abstract: Methods, systems, and devices for wireless communications are described. A base station may transmit a first transport block including a first uplink grant which schedules a first set of uplink shared channel transmissions for the UE. The base station may monitor the channel to detect an energy value for a demodulation reference signal (DMRS) associated with the one or more uplink shared channel transmissions associated with the first uplink grant that is less than a threshold energy value. Based on the relatively low DMRS energy, the base station may modify a size of a second transport block relative to the first transport block, the second transport block including a second uplink grant that schedules a second set of one or more uplink shared channel transmissions for the UE. The base station may then signal the grant for the modified second transport block to the UE or to another device.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: September 24, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Dominique Francois Bressanelli, Ashish Raj Sharma
  • Patent number: 12099788
    Abstract: There is provided a method of predicting performance in electronic design based on machine learning using at least one processor, the method including: providing a first machine learning model configured to predict performance data for an electronic system based on a set of input design parameters for the electronic system; providing a second machine learning model configured to generate a new set of parameter values for the set of input design parameters for the electronic system based on a desired performance data provided for the electronic system; generating, using the second machine learning model, the new set of parameter values for the set of input design parameters for the electronic system based on the desired performance data provided for the electronic system; evaluating the set of input design parameters having the new set of parameter values for the electronic system to obtain an evaluated performance data associated with the set of input design parameters having the new set of parameter values;
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 24, 2024
    Assignee: Agency for Science, Technology and Research
    Inventors: Raju Salahuddin, Rahul Dutta, Kevin Tshun Chuan Chai, Ashish James, Chuan Sheng Foo, Zeng Zeng, Savitha Ramasamy, Vijay Ramaseshan Chandrasekhar
  • Patent number: 12100473
    Abstract: Computer memory arrays employing memory banks and integrated serializer/de-serializer circuits for supporting serialization/de-serialization of read/write data in burst read/write modes, and related methods are disclosed. The memory array can include a serialization circuit configured to convert parallel data streams of read data received from separately switched memory banks into a single, serialized, read data stream in a burst read mode. The memory array can also include a de-serialization circuit configured to convert a received, serialized write data stream on an input bus for a write operation into separate, parallel write data streams to be written simultaneously to the memory banks in a burst write mode.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: September 24, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pramod Kolar, Stephen E. Liles, Ashish A. Bait
  • Patent number: 12099995
    Abstract: A method includes receiving, by a provider computing system from an initiating device, an encrypted network return address of an user device that identifies a network address of the user device; receiving, by the provider computing system and from the user device, an encryption key configured to decrypt the encrypted network return address; decrypting, by the provider computing system, the encrypted network return address using the encryption key; and providing, by the provider computing system, a code to the user device based on the decrypted network return address by transmitting the code to the user device without going through the initiating device.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: September 24, 2024
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Peter Ho, Ashish B. Kurani, Brian M. Pearce, Steven E. Puffer
  • Patent number: 12097502
    Abstract: A cartridge for use with chemical or biological analysis systems, as well as methods of using the same, is provided. The cartridge may include a floating microfluidic plate that is held in the cartridge using one or more floating support brackets that incorporate gaskets that may seal against fluidic ports on the microfluidic plate. The floating support brackets may include indexing features that may align the microfluidic plate with the seals.
    Type: Grant
    Filed: February 11, 2023
    Date of Patent: September 24, 2024
    Assignee: Illumina, Inc.
    Inventors: David Elliott Kaplan, Anthony John de Ruyter, Richard Alan Kelley, Ashish Kumar
  • Publication number: 20240311789
    Abstract: Systems and methods for efficient presentation of payment options at point of sale devices are disclosed. A method may include: identifying a plurality of stored or provisioned payment cards in customer wallets for a merchant; (2) pre-qualifying each of the customers associated with the stored/provisioned payment cards for one or more installment payment options for a purchase from the merchant; and (3) communicating a list of token reference identifiers for stored/provisioned payment cards that have been pre-qualified and the one or more pre-qualified installment payment options to a merchant computer program executed by a merchant backend, wherein the merchant computer program receives a token reference identifier for a stored or provisioned payment card in one of the customer wallets, determines that the token reference identifier is on the list of pre-qualified token reference identifiers, and presents the one or more installment payment options in a checkout user interface.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 19, 2024
    Inventors: Rasik GOYAL, Nikunj TANNA, Ashish P. AJMERA, Sanjay DURGADIN, Riti SINGHAL, Prashant G. PARANJAPE, Selva DHARMARAJ, Josh BERGER, Tushar MISHRA, Sean RODWELL-SIMON, Shashank AITHALA, Hari Kishore CHITNENI, Lakshminarayana BAYAPAREDDY, Rajendra HEBBATAM
  • Publication number: 20240311487
    Abstract: Described herein are hardware monitors arranged to detect illegal firmware instructions in a firmware binary image using a hardware design and one or more formal assertions. The hardware monitors include monitor and detection logic configured to detect when an instantiation of the hardware design has started and/or stopped execution of the firmware and to detect when the instantiation of the hardware design has decoded an illegal firmware instruction. The hardware monitors also include assertion evaluation logic configured to determine whether the firmware binary image comprises an illegal firmware instruction by evaluating one or more assertions that assert that if a stop of firmware execution has been detected, that a decode of an illegal firmware instruction has (or has not) been detected.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 19, 2024
    Inventor: Ashish Darbari
  • Publication number: 20240312085
    Abstract: Reference based digital content stylization techniques are described that enable generation of stylized digital content from a plain text input based on visual style attributes of reference digital content. A content processing system, for instance, receives input digital content including text and reference digital content with a particular visual style. The content processing system determines visual style attributes of the reference digital content, such as a text size, color, font, etc. The content processing system generates an input content classification scheme that includes semantic structure identifiers to classify text of the input digital content, e.g., as a header, subheader, paragraph, and so forth. Based on the input content classification scheme, the content processing system generates stylized digital content by applying the visual style attributes of the reference digital content to the text of the input digital content.
    Type: Application
    Filed: March 14, 2023
    Publication date: September 19, 2024
    Applicant: Adobe Inc.
    Inventors: Ashish Jain, Avil Aneja
  • Publication number: 20240311395
    Abstract: According to one or more embodiments of the disclosure, an example process herein may comprise: obtaining observability data for a computer system for a given time period; determining observability entities from the observability data; converting the observability entities into contextual vertices having associated vertex attributes; determining relationships among the contextual vertices based on correlation of the observability data; selecting a subset of the relationships to be edges based on a quality of the relationships, the edges having associated edge attributes; and generating an observability graph for the observability data for the computer system for the given time period by connecting the contextual vertices via corresponding edges.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 19, 2024
    Inventors: Ashish Kundu, Ramana Rao V. R. Kompella
  • Publication number: 20240312208
    Abstract: An action detection system for dark or low-light videos is provided to detect human action recognition in dark-light situations. The said system includes a novel deep learning architecture that involves an image enhancement module configured to enhance the low-light image frame of action video sequence followed by an action classification module, to classify the actions from the 3D features extracted from the enhanced image frames.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 19, 2024
    Inventor: Ashish GHOSH
  • Publication number: 20240313798
    Abstract: A digital signal processing system to determine a position of a resolver includes a digital signal processor that includes first timer and second timer. The first timer creates a resolver excitation signal from a series of samples and creates an incrementing Crossing signal each time the resolver excitation signal crosses zero. When the Crossing signal has a first value, a multiplexer provides resolver sine signals to an analog to digital converter to convert the resolver sine signal to a series of digital sine samples, and the second timer stores the series of digital sine samples in a sine sample buffer. When the Crossing signal has a second value, the multiplexer provides the resolver cosine signal to the analog to digital converter to convert the resolver cosine signal to a series of digital cosine samples, and the second timer stores the series of digital cosine samples in a buffer.
    Type: Application
    Filed: July 7, 2023
    Publication date: September 19, 2024
    Inventors: Divya Nagaraju, Ashish Vijay, Sundaram Kaliyugavaratharajan, Kannan Thiagarajan
  • Publication number: 20240312690
    Abstract: Embodiments disclosed herein include a motherboard. In an embodiment, the motherboard comprises a first layer with a first trace with a shape. In an embodiment, an insulating layer is provided over the first layer. In an embodiment, a second layer with a second trace with the shape is over the insulating layer. In an embodiment, the second trace is provided directly over the first trace.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 19, 2024
    Inventors: Ashish SHARMA, Arvind SUNDARAM, Vikas MISHRA, Vimal John CYRIL
  • Publication number: 20240314532
    Abstract: Disclosed is a method implemented in an MHS host for managing a plurality of MHS clients. The method includes: monitoring the plurality of MHS clients connected to the MHS host and a data usage of each of the plurality of MHS clients; displaying a list of the plurality of MHS clients and a statistic of the data usage of the plurality of MHS clients; providing an option to manage an MHS client from the plurality of MHS clients; providing, based on a selection of the MHS client, an option to set one at least one of a data limit or a time limit for the metered data usage for the selected MHS client; and controlling the data usage of the selected MHS client based on setting of the data limit or the time limit.
    Type: Application
    Filed: May 23, 2024
    Publication date: September 19, 2024
    Inventors: Madhan Raj KANAGARATHINAM, Manoj R. Hebbbar, Mayank Kumar Sahu, Sri Vinod Palacharla, Jayendra Reddy Kovvuri, Rukmini Gn, Farooq Hussain Sahebzad, Ashish Kumar, Srihari Sriram, Seshu Babu Maddineni, Jungkuk Seo, Ankit Sudhirchandra Vakil
  • Publication number: 20240311779
    Abstract: A computing system may include a network circuit configured to communicate with a third party computing device via a network, one or more interface elements (e.g., application programming interfaces and/or software development kits) providing account open functionality, and an account open circuit configured to: accept, via the interface elements, a set of user data and an account open request for opening a new account with the provider, where the set of user data is received from a user computing device of a user via a third party website or application; establish the new account by generating a set of account data associated with the new account without directing the user to the operating environment of a website or application of the provider; and transmit the set of account data to the third party computing device for use by the third party computing device in a transaction with the user.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Applicant: Wells Fargo Bank, N.A.
    Inventors: Jennifer J. Caceres, Lila Fakhraie, Jennifer Greene, Christopher J. Hirth, Ashish B. Kurani, Andrea Renee Leighton, Margot Lockwood-Stein, Kumaran Perumal, Benjamin Soccorsy, Ronald H. Yang, Young M. Yang
  • Publication number: 20240311202
    Abstract: A command identifying a workload for execution within a cluster architecture is received. Responsive to the command, the workload is deployed to a plurality of different runtime engines on one or more compute nodes within the cluster architecture, wherein the plurality of different runtime engines comprise a container-based runtime engine and a virtual machine (VM)-based runtime engine. Performance metrics are received from each of the plurality of different runtime engines corresponding to execution of the workload.
    Type: Application
    Filed: March 17, 2023
    Publication date: September 19, 2024
    Inventors: Eliyahu Battat, Michey Mehta, Robert Krawitz, Boaz Ben Shabat, Jenifer Abrams, Ashish Kamra
  • Patent number: 12093927
    Abstract: A computer-implemented includes: causing a first interface to be displayed by a mobile device that includes a first selection option; causing a second interface to be displayed by the mobile device that displays an image capture interface; receiving an image from the mobile device based on receiving a second user selection of an image capture function element displayed on the second interface; determining a product associated with a code; receiving a third user selection of the product and a product purchase option associated with the product; transferring a payment for the product to a merchant associated with the product from an account based on information associated with the merchant and the product purchase option; and causing a third interface to be displayed by the mobile device that includes a purchase confirmation that includes order details regarding the product and the product purchase option.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: September 17, 2024
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Ashish Bhoopen Kurani, Melissa Lowry, Stephen M. Ellis
  • Patent number: 12090201
    Abstract: Methods for treating moderate-to-severe or severe atopic dermatitis in a pediatric subject are provided. In one aspect, the methods comprise administering to the subject one or more doses of an interleukin-4 receptor (IL-4R) antagonist, such as an anti-IL-4R antibody or antigen-binding fragment thereof.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: September 17, 2024
    Assignee: Regeneron Pharmaceuticals, Inc.
    Inventors: Ashish Bansal, Neil Graham, Paola Mina-Osorio, John Davis, Mohamed Kamal