Patents by Inventor Ashok K. Kapoor
Ashok K. Kapoor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5943576Abstract: A method is described which forms an MOS transistor having a narrow diffusion region that is smaller than the diffusion region defined using photoresist in a conventional CMOS processing. In one embodiment, LOCOS can be used to form isolation (e.g., shallow trench) between active devices. A polysilicon layer is then deposited and doped either n+ or p+ selectively. The polysilicon layer is then patterned. Next, a dielectric layer and a refractory layer are deposited over the patterned polysilicon layer. Next, a contact hole with a high aspect ratio is defined in the oxide where the transistor will be formed. Angled implant of lightly-doped drain (LDD) regions or graft source/drain regions are formed on two opposite sides of the contact hole. The refractory metal layer is then removed. Spacers are then formed on opposite sidewall of the contact hole. A gate oxide layer is either thermally grown or deposited in the contact, before or after spacer formation.Type: GrantFiled: September 1, 1998Date of Patent: August 24, 1999Assignee: National Semiconductor CorporationInventor: Ashok K. Kapoor
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Patent number: 5889329Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.Type: GrantFiled: August 21, 1995Date of Patent: March 30, 1999Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben, Ashok K. Kapoor, Valeriv B. Kudryavtsev, Alexander E. Andreev, Stanislav V. Aleshin, Alexander S. Podkolzin
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Patent number: 5877045Abstract: A method for depositing a planar dielectric layer between metal traces of a metallization layer of a semiconductor wafer is disclosed. A thin layer of light absorbing material is deposited on the surface of a wafer prior to the formation of metal lines on an overlying patterned metallization layer. A source of directed radiation preferentially heats the light absorbing material while the metal lines reflect the directed radiation and remain largely unheated, thereby allowing dielectric material to be evenly deposited between the metal traces. An isolation layer which insulates the metal traces from the layer of light absorbing material may be required. In some applications, the source of directed radiation is a laser source with a wavelength in the infrared range, and the light absorbing material is a material which absorbs light in this range.Type: GrantFiled: April 10, 1996Date of Patent: March 2, 1999Assignee: LSI Logic CorporationInventor: Ashok K. Kapoor
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Patent number: 5872380Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.Type: GrantFiled: August 21, 1995Date of Patent: February 16, 1999Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben, Ashok K. Kapoor, Valerity B. Kudryavtsev, Alexander E. Andreev, Stanislav V. Aleshin, Alexander S. Podkolzin
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Patent number: 5864165Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.Type: GrantFiled: August 21, 1995Date of Patent: January 26, 1999Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben, Ashok K. Kapoor, Valeriy B. Kudryavtsev, Alexander E. Andreev, Stanislav V. Aleshin, Alexander S. Podkolzin
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Patent number: 5864172Abstract: A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The presence of some gases such as air or an inert gas, or a vacuum, in the porous insulation material reduces the overall dielectric constant of the insulation material, thereby effectively reducing the capacitance of the structure. The porous insulation layer is formed by a chemical vapor deposition of a mixture of the insulation material and a second extractable material; and then subsequently selectively removing the second extractable material, thereby leaving behind a porous matrix of the insulation material, comprising the low dielectric constant insulation layer.Type: GrantFiled: August 13, 1996Date of Patent: January 26, 1999Assignee: LSI Logic CorporationInventors: Ashok K. Kapoor, Nicholas F. Pasch
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Patent number: 5834821Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.Type: GrantFiled: August 21, 1995Date of Patent: November 10, 1998Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben, Ashok K. Kapoor, Valeriy B. Kudryavtsev, Alexander E. Andreev, Stanislav V. Aleshin, Alexander S. Podkolzin
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Patent number: 5835986Abstract: Described is an portion of an integrated circuit structure formed on a semiconductor substrate which provides electrostatic discharge (ESD) protection, utilizing an SCR structure, and also inhibits latchup of the SCR structure. The integrated circuit structure comprises an ESD protection device and an adjoining driver section matched together so that the width dimension of the ESD protection device matches the sum of the length of the adjacent driver section plus twice the width of a doped portion of the substrate forming a guard ring surrounding the driver section. When the length dimension of the MOS structure of the driver section is so maximized by further repeating of the source/gate/drain regions, the physical width dimension of the MOS structure of the driver section may be reduced without reducing the effective width of the MOS structure of the driver section, i.e., the effective width of the MOS structure remains sufficient to permit the required amount of power to be handled by the driver section.Type: GrantFiled: September 6, 1996Date of Patent: November 10, 1998Assignee: LSI Logic CorporationInventors: Hua-Fang Wei, Ashok K. Kapoor
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Patent number: 5822214Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.Type: GrantFiled: August 21, 1995Date of Patent: October 13, 1998Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben, Ashok K. Kapoor, Valeriv B. Kudryavtsev, Alexander E. Andreev, Stanislav V. Aleshin, Alexander S. Podkolzin
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Patent number: 5808330Abstract: A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed.Type: GrantFiled: August 21, 1995Date of Patent: September 15, 1998Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben, Ashok K. Kapoor, Valeriv B. Kudryavtsev, Alexander E. Andreev, Stanislav V. Aleshin, Alexander S. Podkolzin
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Patent number: 5801422Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.Type: GrantFiled: August 21, 1995Date of Patent: September 1, 1998Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben, Ashok K. Kapoor, Valeriy B. Kudryavtsev, Alexander E. Andreev, Stanislav V. Aleshin, Alexander S. Podkolzin
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Patent number: 5789783Abstract: A first metal layer is formed on a substrate of an integrated circuit and electrically interconnects a microelectronic device and an Input/Output (I/O) pad. A second metal layer is insulated from the first metal layer by a dielectric layer, and is connected directly only to the pad. A plurality of vias are formed through the dielectric layer, and electrically interconnect the first and second metal layers such that current can flow between the device and the pad through both metal layers and the vias. A higher scale of circuit integration is made possible by reducing the widths of the metal layers without reducing their combined current carrying capacity. An Electrostatic Discharge (ESD) protection device is connected to one or both of the first and second metal layers such that current can flow from the pad to the protection device during an ESD event through both metal layers and the vias.Type: GrantFiled: April 2, 1996Date of Patent: August 4, 1998Assignee: LSI Logic CorporationInventors: Ratan K. Choudhury, Ashok K. Kapoor, Satish Menon
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Patent number: 5789770Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.Type: GrantFiled: August 21, 1995Date of Patent: August 4, 1998Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben, Ashok K. Kapoor, Valeriv B. Kudryavtsev, Alexander E. Andreev, Stanislav V. Aleshin, Alexander S. Podkolzin
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Patent number: 5780350Abstract: LDD regions of a MOSFET device in an integrated circuit structure are formed in a semiconductor substrate, after formation of the source/drain regions of the MOSFET device by forming spacers on the sidewalls of the gate electrode prior to doping of the substrate to form source/drain regions by implantation and annealing/activating. The sidewall spacers are then removed, and the portion of the substrate exposed by removal of the spacers is then lightly doped to form the desired LDD regions in the substrate between the respective source/drain regions and a channel region of the substrate below the gate oxide. In this manner, the dopant used to form the LDD regions is not exposed to the heat used to anneal and activate the implanted source/drain regions.Type: GrantFiled: January 30, 1997Date of Patent: July 14, 1998Assignee: LSI Logic CorporationInventor: Ashok K. Kapoor
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Patent number: 5780347Abstract: A method and apparatus of forming local interconnects in a MOS process deposits a layer of polysilicon over an entire region after several conventional MOS processing steps. The region is then masked to provide protected regions and unprotected regions. The mask may be used to define local interconnects and other conductive elements such as the source and drain contact regions for a MOS transistor. After masking, the region is bombarded with atoms to enhance the oxidation potential of the unprotected regions. The masking is removed and the substrate is then exposed to oxidizing conditions which cause the unprotected regions to rapidly oxidize to form a thick oxide layer. The formerly protected polysilicon regions may then be doped to render them conductive.Type: GrantFiled: May 20, 1996Date of Patent: July 14, 1998Inventor: Ashok K. Kapoor
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Patent number: 5777360Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclose. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.Type: GrantFiled: August 21, 1995Date of Patent: July 7, 1998Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben, Ashok K. Kapoor, Valeriy B. Kudryavtsev, Alexander E. Andreev, Stanislav V. Aleshin, Alexander S. Podkolzin
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Patent number: 5770492Abstract: A method is provided for forming planar, self-aligned spaced-apart wells without a high temperature oxidation step to form an ion barrier. The method comprises preparing a substrate with a silicon dioxide-polysilicon-silicon dioxide barrier layer that can be etched to expose different sublayers of the barrier at selected junctures in the production process. A single masking step defines the location of a first set of wells on the prepared substrate. The outer silicon dioxide layer is etched to expose the polysilicon layer at the selected locations, and the substrate is implanted to form the first set of wells. Following ion implantation, the substrate photo-resist is removed, and the substrate is exposed to a germanium-silicon mixture under conditions selected to preferentially deposit a germanium-silicon alloy barrier layer on the exposed polysilicon layer.Type: GrantFiled: December 18, 1996Date of Patent: June 23, 1998Assignee: LSI Logic CorporationInventor: Ashok K. Kapoor
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Patent number: 5763302Abstract: A method is provided for forming planar, self-aligned spaced-apart wells without a high temperature oxidation step to form an ion barrier. The method comprises preparing a substrate with a silicon dioxide-polysilicon-silicon dioxide barrier layer that can be etched to expose different sublayers of the barrier at selected junctures in the production process. A single masking step defines the location of a first set of wells on the prepared substrate. The outer silicon dioxide layer is etched to expose the polysilicon layer at the selected locations, and the substrate is implanted to form the first set of wells. Following ion implantation, the substrate photo-resist is removed, and the substrate is exposed to a germanium-silicon mixture under conditions selected to preferentially deposit a germanium-silicon alloy barrier layer on the exposed polysilicon layer.Type: GrantFiled: August 20, 1996Date of Patent: June 9, 1998Assignee: LSI Logic CorporationInventor: Ashok K. Kapoor
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Patent number: 5756395Abstract: A process for forming an integrated circuit structure is described wherein individual integrated circuit devices such as MOS or bipolar transistors are constructed on and in a semiconductor substrate and one or more layers of metal interconnects are constructed on and in a second substrate, preferably of similar thickness, and the two substrates are then aligned and bonded together to thereby provide electrical interconnections of individual integrated circuit devices on the semiconductor substrate with appropriate metal interconnects on the second substrate to provide the desired integrated circuit structure.Type: GrantFiled: August 18, 1995Date of Patent: May 26, 1998Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, Ashok K. Kapoor
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Patent number: 5742086Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.Type: GrantFiled: August 21, 1995Date of Patent: April 21, 1998Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben, Ashok K. Kapoor, Valeriy B. Kudryavtsev, Alexander E. Andreev, Stanislav V. Aleshin, Alexander S. Podkolzin