Abstract: A system configured to protect valuable, sensitive, or electro-mechanical equipment during cleaning of the equipment can include a cover having a single opening leading to an interior cavity. The cover can be waterproof. A plate can be permanently attached to the cable of the equipment. An outer periphery of the plate can be approximately the same size as an inner periphery of the opening. The plate can be configured to sealingly fit within the single opening. The system can include a latching mechanism configured to sealingly attach the plate to the cover.

Abstract: A system and method for generating a user query based on a target context aware token. The method encompasses initiating, by a processing unit [102], a search engine. The method further comprises receiving, via an input unit [104], a user input at the search engine. The method further recommends, by the processing unit [102], a set of context aware tokens based at least on the user input. Further the method encompasses selecting, by the processing unit [102], a target context aware token from the set of context aware tokens based on a user selection. The method thereafter comprises appending, by the processing unit [102], the target context aware token to the user input in the search engine. Further the method comprises generating, by the processing unit [102], the user query based on appending the target context aware token to the user input.

Abstract: A system and method for providing an information related to similar product of a product. The method encompasses receiving at least one numeric query comprising numeric part/s and non-numeric part/s. The method thereafter comprises identifying an availability of product/s corresponding to the at least one numeric query. Further, the method encompasses generating a positive indication and/or a negative indication based on the identification of the availability of the product/s. The method thereafter encompasses identifying at least one numeric alternate for the numeric part/s based on the negative indication, an intent of the at least one non-numeric part of said each numeric query and an availability of similar product/s of the product/s. Further the method comprises providing an information related to the similar product/s based on the at least one numeric alternate of the numeric part/s and the availability of the similar product/s.

Abstract: An apparatus includes an image sensor having a light sensing region, the light sensing region being partitioned into a plurality of sub-regions, a first sub-region of the plurality of sub-regions has a first size, a second sub-region of the plurality of sub-regions has a second size different from the first size, and the second sub-region partially overlaps with the first sub-region. The apparatus further includes a processor coupled with the image sensor, wherein the processor includes a plurality of pixel processing units, and each processing unit of the plurality of processing units is configured to generate a processed image based on an image captured by a corresponding sub-region of the plurality of sub-regions. The apparatus further includes a plurality of lenses configured to focus incident light onto the image sensor.

Abstract: A method for dynamic frequency scaling (DFS) on the electronic systems level (ESL). The method can run in a virtual environment and dynamically scale the frequency of a virtual component based on a first transaction time and a second transaction time.

Abstract: An apparatus includes an image sensor having a light sensing region, the light sensing region being partitioned into a plurality of sub-regions, a first sub-region of the plurality of sub-regions has a first size, a second sub-region of the plurality of sub-regions has a second size different from the first size, and the second sub-region partially overlaps with the first sub-region. The apparatus further includes a processor coupled with the image sensor, wherein the processor includes a plurality of pixel processing units, and each processing unit of the plurality of processing units is configured to generate a processed image based on an image captured by a corresponding sub-region of the plurality of sub-regions. The apparatus further includes a plurality of lenses configured to focus incident light onto the image sensor.

Abstract: An apparatus comprises an integrated circuit and at least one lens. The integrated circuit comprises an image sensor having a light sensing region. The light sensing region is partitioned into sub-regions. The integrated circuit also comprises a processor coupled with and beneath the image sensor. The processor is configured to generate a first processed image based on an image captured by one sub-region, and a second processed image based on another image captured by another sub-region. The first processed image and the second processed image are generated based on a pixel correction process executed by the processor which corrects one or more of the image or the another image based on a predefined light reception factor associated with the sub-regions. The image sensor is configured to receive light via the light sensing region through the at least one lens.

Abstract: A method for dynamic frequency scaling (DFS) on the electronic systems level (ESL). The method can run in a virtual environment and dynamically scale the frequency of a virtual component based on a first transaction time and a second transaction time.

Abstract: A method for dynamic frequency scaling (DFS) on the electronic systems level (ESL). The method can run in a virtual environment and dynamically scale the frequency of a virtual component based on a first transaction time and a second transaction time.

Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

Abstract: Provided is a system that includes a monitoring unit, processing units, and peripheral units. Each of the processing units is linked to the monitoring unit and each of the peripheral units is also linked to the monitoring unit. Each of the processing units is configured to transmit requests to and subsequently receive responses from at least one of the peripheral units through the monitoring unit. The monitoring unit is configured to measure and store delays between the responses and the respective requests.

Abstract: A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.

Abstract: A method of transmitting data is disclosed. At least one system block of a system-on-chip (SoC) is modeled at an untimed functional level in first and second untimed functional models. First and second transaction level (TL) models of the at least one system block system block are modeled at a transaction level (TL) using the first and second untimed functional models, respectively. First and second cycle accurate (CA) models are modeled at a cycle accurate (CA) level using the first and second TL models, respectively. Data is transmitted from the first untimed functional model to the first CA model, from the first CA model to the second CA model via a CA bus, and from the second CA model to the second untimed functional model.

Abstract: A method includes receiving a design of an interposer having nets, probe pads, and micro-bumps. The nets connect the micro-bumps. The probe pads are initially unconnected to the nets. The method further includes initializing a first set to logically include the nets; processing the first set such that every net interconnecting more than two micro-bumps is divided into a plurality of nets and every two micro-bumps are interconnected by one net; calculating an untested length for each net in the first set; selecting a net N from the first set wherein the net N has the maximum untested length in the first set, the net N representing at least a portion of a net P of the nets; selecting a pair of probe pads that are unconnected to the nets; and connecting the pair of probe pads to the net P by two dummy nets.

Abstract: A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit. The KGL test circuit includes a scan segment, and a plurality of inputs, outputs, and multiplexers coupled to the scan segment. The KGL test circuit further includes a plurality of control elements such that scan testing of the stacked IC may be conducted on a layer-by-layer basis.

Abstract: An apparatus comprises an integrated circuit and at least one lens. The integrated circuit comprises an image sensor having a light sensing region. The light sensing region is partitioned into sub-regions. The integrated circuit also comprises a processor coupled with and beneath the image sensor. The processor is configured to generate a first processed image based on an image captured by one sub-region, and a second processed image based on another image captured by another sub-region. The first processed image and the second processed image are generated based on a pixel correction process executed by the processor which corrects one or more of the image or the another image based on a predefined light reception factor associated with the sub-regions. The image sensor is configured to receive light via the light sensing region through the at least one lens.

Abstract: A method includes receiving a design of an interposer having nets, probe pads, and micro-bumps. The nets connect the micro-bumps. The probe pads are initially unconnected to the nets. The method further includes initializing a first set to logically include the nets; processing the first set such that every net interconnecting more than two micro-bumps is divided into a plurality of nets and every two micro-bumps are interconnected by one net; calculating an untested length for each net in the first set; selecting a net N from the first set wherein the net N has the maximum untested length in the first set, the net N representing at least a portion of a net P of the nets; selecting a pair of probe pads that are unconnected to the nets; and connecting the pair of probe pads to the net P by two dummy nets.

Abstract: A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit. The KGL test circuit includes a scan segment, and a plurality of inputs, outputs, and multiplexers coupled to the scan segment. The KGL test circuit further includes a plurality of control elements such that scan testing of the stacked IC may be conducted on a layer-by-layer basis.

Abstract: Provided is a method of assigning a first set of probe pads to an interposer for maximizing a defect coverage for the interposer. The interposer includes a second set of nets and the defect coverage is based on a ratio between a tested net length and an overall net length. The method includes processing the second set such that every net interconnecting more than two micro-bumps is divided into a plurality of nets and every two of the more than two micro-bumps are interconnected by one of the plurality of nets. The method further includes calculating an untested length of each net in the second set; selecting a first net from the second set with the maximum untested length; selecting two probe pads from the first set based on a user-defined cost function; and connecting the two probe pads to the first net with two dummy nets.

Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.