Patents by Inventor Ashok Pachamuthu

Ashok Pachamuthu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11929349
    Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, Ashok Pachamuthu
  • Publication number: 20220169905
    Abstract: A sintering powder comprising: a particulate having a mean longest diameter of less than 10 microns, wherein at least some of the particles forming the particulate comprise a metal at least partially coated with a capping agent. A sintering paste and sintering film comprising the sintering powder. A method for making a sintered joint by sintering the sintering powder, paste, or film in the vicinity of two or more workpieces.
    Type: Application
    Filed: October 4, 2021
    Publication date: June 2, 2022
    Applicant: Alpha Assembly Solutions Inc.
    Inventors: Shamik Ghosal, Ranjit Pandher, Oscar Khaselev, Ravi Bhatkal, Rahul Raut, Bawa Singh, Morgana de Avila Ribas, Siuli Sarkar, Sutapa Mukherjee, Sathish Kumar, Remya Chandran, Pavan Vishwanath, Ashok Pachamuthu, Monnir Boureghda, Nitin Desai, Anna Lifton, Nirmalya Kumar Chaki
  • Patent number: 11162007
    Abstract: A sintering powder comprising: a particulate having a mean longest diameter of less than 10 microns, wherein at least some of the particles forming the particulate comprise a metal at least partially coated with a capping agent. A sintering paste and sintering film comprising the sintering powder. A method for making a sintered joint by sintering the sintering powder, paste, or film in the vicinity of two or more workpieces.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: November 2, 2021
    Assignee: Alpha Assembly Solutions Inc.
    Inventors: Shamik Ghosal, Ranjit Pandher, Oscar Khaselev, Ravi Bhatkal, Rahul Raut, Bawa Singh, Morgana de Avila Ribas, Siuli Sarkar, Sutapa Mukherjee, Sathish Kumar, Remya Chandran, Pavan Vishwanath, Ashok Pachamuthu, Monnir Boureghda, Nitin Desai, Anna Lifton, Nirmalya Kumar Chaki
  • Publication number: 20210272932
    Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.
    Type: Application
    Filed: May 13, 2021
    Publication date: September 2, 2021
    Inventors: Chan H. Yoo, Ashok Pachamuthu
  • Patent number: 11037910
    Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, Ashok Pachamuthu
  • Publication number: 20200350293
    Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Chan H. Yoo, Ashok Pachamuthu
  • Patent number: 10593568
    Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, John F. Kaeding, Ashok Pachamuthu, Mark E. Tuttle
  • Patent number: 10586780
    Abstract: Semiconductor device modules may include a semiconductor die and posts located laterally adjacent to the semiconductor die. A first encapsulant may laterally surround the semiconductor die and the posts. Electrical connectors may extend laterally from the posts, over the first encapsulant, to bond pads on an active surface of the semiconductor die. A protective material may cover the electrical connectors. A second encapsulant may cover the protective material and the electrical connectors. The second encapsulant may be in direct contact with the first encapsulant, the electrical connectors, and the protective material.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
  • Publication number: 20190252342
    Abstract: Semiconductor device modules may include a semiconductor die and posts located laterally adjacent to the semiconductor die. A first encapsulant may laterally surround the semiconductor die and the posts. Electrical connectors may extend laterally from the posts, over the first encapsulant, to bond pads on an active surface of the semiconductor die. A protective material may cover the electrical connectors. A second encapsulant may cover the protective material and the electrical connectors. The second encapsulant may be in direct contact with the first encapsulant, the electrical connectors, and the protective material.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
  • Publication number: 20190194517
    Abstract: A sintering powder comprising: a particulate having a mean longest diameter of less than 10 microns, wherein at least some of the particles forming the particulate comprise a metal at least partially coated with a capping agent. A sintering paste and sintering film comprising the sintering powder. A method for making a sintered joint by sintering the sintering powder, paste, or film in the vicinity of two or more workpieces.
    Type: Application
    Filed: March 1, 2019
    Publication date: June 27, 2019
    Inventors: Shamik Ghosal, Ranjit Pandher, Oscar Khaselev, Ravi Bhatkal, Rahul Raut, Bawa Singh, Morgana de Avila Ribas, Siuli Sarkar, Sutapa Mukherjee, Sathish Kumar, Remya Chandran, Pavan Vishwanath, Ashok Pachamuthu, Monnir Boureghda, Nitin Desai, Anna Lifton, Nirmalya Kumar Chaki
  • Patent number: 10325874
    Abstract: Semiconductor device modules may include a redistribution layer and a first semiconductor die. A second semiconductor die may be located on the first semiconductor die. Posts may be located laterally adjacent to the first semiconductor die and the second semiconductor die. A first encapsulant may at least laterally surround the first semiconductor die, the second semiconductor die, and the posts. Electrical connectors may extend laterally from the posts, over the first encapsulant, to bond pads on a second active surface of the second semiconductor die. A protective material may cover the electrical connectors. A second encapsulant may be located over the protective material and the electrical connectors. The second encapsulant may be in direct contact with the first encapsulant, the electrical connectors, and the protective material. Conductive bumps may be connected to the redistribution layer on a side of the redistribution layer opposite the first semiconductor die.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
  • Patent number: 10259980
    Abstract: A sintering powder comprising: a particulate having a mean longest diameter of less than 10 microns, wherein at least some of the particles forming the particulate comprise a metal at least partially coated with a capping agent. A sintering paste and sintering film comprising the sintering powder. A method for making a sintered joint by sintering the sintering powder, paste, or film in the vicinity of two or more workpieces.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: April 16, 2019
    Assignee: Alpha Assembly Solutions Inc.
    Inventors: Shamik Ghosal, Ranjit Pandher, Oscar Khaselev, Ravi Bhatkal, Rahul Raut, Bawa Singh, Morgana Ribas, Siuli Sarkar, Sutapa Mukherjee, Sathish Kumar, Remya Chandran, Pavan Vishwanath, Ashok Pachamuthu, Monnir Boureghda, Nitin Desai, Anna Lifton, Nirmalya Kumar Chaki
  • Publication number: 20190067233
    Abstract: Semiconductor device modules may include a redistribution layer and a first semiconductor die. A second semiconductor die may be located on the first semiconductor die. Posts may be located laterally adjacent to the first semiconductor die and the second semiconductor die. A first encapsulant may at least laterally surround the first semiconductor die, the second semiconductor die, and the posts. Electrical connectors may extend laterally from the posts, over the first encapsulant, to bond pads on a second active surface of the second semiconductor die. A protective material may cover the electrical connectors. A second encapsulant may be located over the protective material and the electrical connectors. The second encapsulant may be in direct contact with the first encapsulant, the electrical connectors, and the protective material. Conductive bumps may be connected to the redistribution layer on a side of the redistribution layer opposite the first semiconductor die.
    Type: Application
    Filed: October 30, 2018
    Publication date: February 28, 2019
    Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
  • Publication number: 20190067034
    Abstract: Semiconductor devices with redistribution structures that do not include pre-formed substrates and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die attached to a redistribution structure and electrically coupled to the redistribution structure via a plurality of wire bonds. The semiconductor device can also include one or more second semiconductor dies stacked on the first semiconductor die, wherein one or more of the first and second semiconductor dies are electrically coupled to the redistribution structure via a plurality of wire bonds. The semiconductor device can also include a molded material over the first and/or second semiconductor dies and a surface of the redistribution structure.
    Type: Application
    Filed: August 24, 2017
    Publication date: February 28, 2019
    Inventors: Ashok Pachamuthu, Chan H. Yoo, John F. Kaeding
  • Publication number: 20190067038
    Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.
    Type: Application
    Filed: September 6, 2018
    Publication date: February 28, 2019
    Inventors: Chan H. Yoo, John F. Kaeding, Ashok Pachamuthu, Mark E. Tuttle
  • Publication number: 20190067248
    Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.
    Type: Application
    Filed: August 24, 2017
    Publication date: February 28, 2019
    Inventors: Chan H. Yoo, Ashok Pachamuthu
  • Publication number: 20190035755
    Abstract: Methods of making semiconductor device modules may involve forming holes in a sacrificial material and placing an electrically conductive material in the holes. The sacrificial material may be removed to expose posts of the electrically conductive material. A stack of semiconductor dice may be placed between at least two of the posts after removing the sacrificial material, one of the semiconductor dice of the stack including an active surface facing in a direction opposite a direction in which another active surface of another of the semiconductor dice of the stack. The posts and the stack of semiconductor dice may be at least laterally encapsulated in an encapsulant. Bond pads of the one of the semiconductor dice may be electrically connected to corresponding posts after at least laterally encapsulating the posts and the stack of semiconductor dice.
    Type: Application
    Filed: July 26, 2017
    Publication date: January 31, 2019
    Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
  • Patent number: 10192843
    Abstract: Methods of making semiconductor device modules may involve forming holes in a sacrificial material and placing an electrically conductive material in the holes. The sacrificial material may be removed to expose posts of the electrically conductive material. A stack of semiconductor dice may be placed between at least two of the posts after removing the sacrificial material, one of the semiconductor dice of the stack including an active surface facing in a direction opposite a direction in which another active surface of another of the semiconductor dice of the stack. The posts and the stack of semiconductor dice may be at least laterally encapsulated in an encapsulant. Bond pads of the one of the semiconductor dice may be electrically connected to corresponding posts after at least laterally encapsulating the posts and the stack of semiconductor dice.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: January 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
  • Patent number: 10103038
    Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: October 16, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, John F. Kaeding, Ashok Pachamuthu, Mark E. Tuttle
  • Publication number: 20150353804
    Abstract: A sintering powder comprising: a particulate having a mean longest diameter of less than 10 microns, wherein at least some of the particles forming the particulate comprise a metal at least partially coated with a capping agent. A sintering paste and sintering film comprising the sintering powder. A method for making a sintered joint by sintering the sintering powder, paste, or film in the vicinity of two or more workpieces.
    Type: Application
    Filed: October 29, 2013
    Publication date: December 10, 2015
    Applicant: ALPHA METALS, INC.
    Inventors: Shamik Ghosal, Ranjit Pandher, Oscar Khaselev, Ravi Bhatkal, Rahul Raut, Bawa Singh, Morgana Ribas, Siuli Sarkar, Sutapa Mukherjee, Sathish Kumar, Remya Chandran, Pavan Vishwanath, Ashok Pachamuthu, Monnir Boureghda, Nitin Desai, Anna Lifton, Nirmalya Kumar Chaki