Patents by Inventor Ashok Pachamuthu
Ashok Pachamuthu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929349Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.Type: GrantFiled: May 13, 2021Date of Patent: March 12, 2024Assignee: Micron Technology, Inc.Inventors: Chan H. Yoo, Ashok Pachamuthu
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Publication number: 20220169905Abstract: A sintering powder comprising: a particulate having a mean longest diameter of less than 10 microns, wherein at least some of the particles forming the particulate comprise a metal at least partially coated with a capping agent. A sintering paste and sintering film comprising the sintering powder. A method for making a sintered joint by sintering the sintering powder, paste, or film in the vicinity of two or more workpieces.Type: ApplicationFiled: October 4, 2021Publication date: June 2, 2022Applicant: Alpha Assembly Solutions Inc.Inventors: Shamik Ghosal, Ranjit Pandher, Oscar Khaselev, Ravi Bhatkal, Rahul Raut, Bawa Singh, Morgana de Avila Ribas, Siuli Sarkar, Sutapa Mukherjee, Sathish Kumar, Remya Chandran, Pavan Vishwanath, Ashok Pachamuthu, Monnir Boureghda, Nitin Desai, Anna Lifton, Nirmalya Kumar Chaki
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Patent number: 11162007Abstract: A sintering powder comprising: a particulate having a mean longest diameter of less than 10 microns, wherein at least some of the particles forming the particulate comprise a metal at least partially coated with a capping agent. A sintering paste and sintering film comprising the sintering powder. A method for making a sintered joint by sintering the sintering powder, paste, or film in the vicinity of two or more workpieces.Type: GrantFiled: March 1, 2019Date of Patent: November 2, 2021Assignee: Alpha Assembly Solutions Inc.Inventors: Shamik Ghosal, Ranjit Pandher, Oscar Khaselev, Ravi Bhatkal, Rahul Raut, Bawa Singh, Morgana de Avila Ribas, Siuli Sarkar, Sutapa Mukherjee, Sathish Kumar, Remya Chandran, Pavan Vishwanath, Ashok Pachamuthu, Monnir Boureghda, Nitin Desai, Anna Lifton, Nirmalya Kumar Chaki
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Publication number: 20210272932Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.Type: ApplicationFiled: May 13, 2021Publication date: September 2, 2021Inventors: Chan H. Yoo, Ashok Pachamuthu
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Patent number: 11037910Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.Type: GrantFiled: July 20, 2020Date of Patent: June 15, 2021Assignee: Micron Technology, Inc.Inventors: Chan H. Yoo, Ashok Pachamuthu
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Publication number: 20200350293Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.Type: ApplicationFiled: July 20, 2020Publication date: November 5, 2020Inventors: Chan H. Yoo, Ashok Pachamuthu
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Patent number: 10593568Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.Type: GrantFiled: September 6, 2018Date of Patent: March 17, 2020Assignee: Micron Technology, Inc.Inventors: Chan H. Yoo, John F. Kaeding, Ashok Pachamuthu, Mark E. Tuttle
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Patent number: 10586780Abstract: Semiconductor device modules may include a semiconductor die and posts located laterally adjacent to the semiconductor die. A first encapsulant may laterally surround the semiconductor die and the posts. Electrical connectors may extend laterally from the posts, over the first encapsulant, to bond pads on an active surface of the semiconductor die. A protective material may cover the electrical connectors. A second encapsulant may cover the protective material and the electrical connectors. The second encapsulant may be in direct contact with the first encapsulant, the electrical connectors, and the protective material.Type: GrantFiled: April 29, 2019Date of Patent: March 10, 2020Assignee: Micron Technology, Inc.Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
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Publication number: 20190252342Abstract: Semiconductor device modules may include a semiconductor die and posts located laterally adjacent to the semiconductor die. A first encapsulant may laterally surround the semiconductor die and the posts. Electrical connectors may extend laterally from the posts, over the first encapsulant, to bond pads on an active surface of the semiconductor die. A protective material may cover the electrical connectors. A second encapsulant may cover the protective material and the electrical connectors. The second encapsulant may be in direct contact with the first encapsulant, the electrical connectors, and the protective material.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
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Publication number: 20190194517Abstract: A sintering powder comprising: a particulate having a mean longest diameter of less than 10 microns, wherein at least some of the particles forming the particulate comprise a metal at least partially coated with a capping agent. A sintering paste and sintering film comprising the sintering powder. A method for making a sintered joint by sintering the sintering powder, paste, or film in the vicinity of two or more workpieces.Type: ApplicationFiled: March 1, 2019Publication date: June 27, 2019Inventors: Shamik Ghosal, Ranjit Pandher, Oscar Khaselev, Ravi Bhatkal, Rahul Raut, Bawa Singh, Morgana de Avila Ribas, Siuli Sarkar, Sutapa Mukherjee, Sathish Kumar, Remya Chandran, Pavan Vishwanath, Ashok Pachamuthu, Monnir Boureghda, Nitin Desai, Anna Lifton, Nirmalya Kumar Chaki
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Patent number: 10325874Abstract: Semiconductor device modules may include a redistribution layer and a first semiconductor die. A second semiconductor die may be located on the first semiconductor die. Posts may be located laterally adjacent to the first semiconductor die and the second semiconductor die. A first encapsulant may at least laterally surround the first semiconductor die, the second semiconductor die, and the posts. Electrical connectors may extend laterally from the posts, over the first encapsulant, to bond pads on a second active surface of the second semiconductor die. A protective material may cover the electrical connectors. A second encapsulant may be located over the protective material and the electrical connectors. The second encapsulant may be in direct contact with the first encapsulant, the electrical connectors, and the protective material. Conductive bumps may be connected to the redistribution layer on a side of the redistribution layer opposite the first semiconductor die.Type: GrantFiled: October 30, 2018Date of Patent: June 18, 2019Assignee: Micron Technology, Inc.Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
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Patent number: 10259980Abstract: A sintering powder comprising: a particulate having a mean longest diameter of less than 10 microns, wherein at least some of the particles forming the particulate comprise a metal at least partially coated with a capping agent. A sintering paste and sintering film comprising the sintering powder. A method for making a sintered joint by sintering the sintering powder, paste, or film in the vicinity of two or more workpieces.Type: GrantFiled: October 29, 2013Date of Patent: April 16, 2019Assignee: Alpha Assembly Solutions Inc.Inventors: Shamik Ghosal, Ranjit Pandher, Oscar Khaselev, Ravi Bhatkal, Rahul Raut, Bawa Singh, Morgana Ribas, Siuli Sarkar, Sutapa Mukherjee, Sathish Kumar, Remya Chandran, Pavan Vishwanath, Ashok Pachamuthu, Monnir Boureghda, Nitin Desai, Anna Lifton, Nirmalya Kumar Chaki
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Publication number: 20190067233Abstract: Semiconductor device modules may include a redistribution layer and a first semiconductor die. A second semiconductor die may be located on the first semiconductor die. Posts may be located laterally adjacent to the first semiconductor die and the second semiconductor die. A first encapsulant may at least laterally surround the first semiconductor die, the second semiconductor die, and the posts. Electrical connectors may extend laterally from the posts, over the first encapsulant, to bond pads on a second active surface of the second semiconductor die. A protective material may cover the electrical connectors. A second encapsulant may be located over the protective material and the electrical connectors. The second encapsulant may be in direct contact with the first encapsulant, the electrical connectors, and the protective material. Conductive bumps may be connected to the redistribution layer on a side of the redistribution layer opposite the first semiconductor die.Type: ApplicationFiled: October 30, 2018Publication date: February 28, 2019Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
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Publication number: 20190067034Abstract: Semiconductor devices with redistribution structures that do not include pre-formed substrates and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die attached to a redistribution structure and electrically coupled to the redistribution structure via a plurality of wire bonds. The semiconductor device can also include one or more second semiconductor dies stacked on the first semiconductor die, wherein one or more of the first and second semiconductor dies are electrically coupled to the redistribution structure via a plurality of wire bonds. The semiconductor device can also include a molded material over the first and/or second semiconductor dies and a surface of the redistribution structure.Type: ApplicationFiled: August 24, 2017Publication date: February 28, 2019Inventors: Ashok Pachamuthu, Chan H. Yoo, John F. Kaeding
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Publication number: 20190067038Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.Type: ApplicationFiled: September 6, 2018Publication date: February 28, 2019Inventors: Chan H. Yoo, John F. Kaeding, Ashok Pachamuthu, Mark E. Tuttle
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Publication number: 20190067248Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.Type: ApplicationFiled: August 24, 2017Publication date: February 28, 2019Inventors: Chan H. Yoo, Ashok Pachamuthu
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Publication number: 20190035755Abstract: Methods of making semiconductor device modules may involve forming holes in a sacrificial material and placing an electrically conductive material in the holes. The sacrificial material may be removed to expose posts of the electrically conductive material. A stack of semiconductor dice may be placed between at least two of the posts after removing the sacrificial material, one of the semiconductor dice of the stack including an active surface facing in a direction opposite a direction in which another active surface of another of the semiconductor dice of the stack. The posts and the stack of semiconductor dice may be at least laterally encapsulated in an encapsulant. Bond pads of the one of the semiconductor dice may be electrically connected to corresponding posts after at least laterally encapsulating the posts and the stack of semiconductor dice.Type: ApplicationFiled: July 26, 2017Publication date: January 31, 2019Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
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Patent number: 10192843Abstract: Methods of making semiconductor device modules may involve forming holes in a sacrificial material and placing an electrically conductive material in the holes. The sacrificial material may be removed to expose posts of the electrically conductive material. A stack of semiconductor dice may be placed between at least two of the posts after removing the sacrificial material, one of the semiconductor dice of the stack including an active surface facing in a direction opposite a direction in which another active surface of another of the semiconductor dice of the stack. The posts and the stack of semiconductor dice may be at least laterally encapsulated in an encapsulant. Bond pads of the one of the semiconductor dice may be electrically connected to corresponding posts after at least laterally encapsulating the posts and the stack of semiconductor dice.Type: GrantFiled: July 26, 2017Date of Patent: January 29, 2019Assignee: Micron Technology, Inc.Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
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Patent number: 10103038Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.Type: GrantFiled: August 24, 2017Date of Patent: October 16, 2018Assignee: Micron Technology, Inc.Inventors: Chan H. Yoo, John F. Kaeding, Ashok Pachamuthu, Mark E. Tuttle
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Publication number: 20150353804Abstract: A sintering powder comprising: a particulate having a mean longest diameter of less than 10 microns, wherein at least some of the particles forming the particulate comprise a metal at least partially coated with a capping agent. A sintering paste and sintering film comprising the sintering powder. A method for making a sintered joint by sintering the sintering powder, paste, or film in the vicinity of two or more workpieces.Type: ApplicationFiled: October 29, 2013Publication date: December 10, 2015Applicant: ALPHA METALS, INC.Inventors: Shamik Ghosal, Ranjit Pandher, Oscar Khaselev, Ravi Bhatkal, Rahul Raut, Bawa Singh, Morgana Ribas, Siuli Sarkar, Sutapa Mukherjee, Sathish Kumar, Remya Chandran, Pavan Vishwanath, Ashok Pachamuthu, Monnir Boureghda, Nitin Desai, Anna Lifton, Nirmalya Kumar Chaki