Patents by Inventor Ashok S. Prabhu
Ashok S. Prabhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240047376Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.Type: ApplicationFiled: September 21, 2023Publication date: February 8, 2024Inventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
-
Patent number: 11810867Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.Type: GrantFiled: August 23, 2022Date of Patent: November 7, 2023Assignee: Invensas LLCInventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
-
Publication number: 20230059375Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.Type: ApplicationFiled: August 23, 2022Publication date: February 23, 2023Inventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
-
Patent number: 11462483Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.Type: GrantFiled: December 16, 2019Date of Patent: October 4, 2022Assignee: Invensas LLCInventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
-
Publication number: 20200118939Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Applicant: Invensas CorporationInventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
-
Patent number: 10559537Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.Type: GrantFiled: September 10, 2018Date of Patent: February 11, 2020Assignee: Invensas CorporationInventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
-
Patent number: 10490528Abstract: Apparatuses relating generally to a vertically integrated microelectronic package are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface. A first microelectronic device is coupled to the upper surface of the substrate. The first microelectronic device is a passive microelectronic device. First wire bond wires are coupled to and extend away from the upper surface of the substrate. Second wire bond wires are coupled to and extend away from an upper surface of the first microelectronic device. The second wire bond wires are shorter than the first wire bond wires. A second microelectronic device is coupled to upper ends of the first wire bond wires and the second wire bond wires. The second microelectronic device is located above the first microelectronic device and at least partially overlaps the first microelectronic device.Type: GrantFiled: January 12, 2016Date of Patent: November 26, 2019Assignee: Invensas CorporationInventors: Ashok S. Prabhu, Abiola Awujoola, Wael Zohni, Willmar Subido
-
Patent number: 10354976Abstract: Dies-on-package devices and methods therefor are disclosed. In a dies-on-package device, a first IC die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with respect to the first IC die. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first IC die, and around bases and shafts of the conductive lines. A plurality of second IC dies is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. The plurality of second IC dies are respectively coupled to the sets of the conductive lines in middle third portions respectively of the plurality of second IC dies for corresponding fan-in regions thereof.Type: GrantFiled: December 28, 2016Date of Patent: July 16, 2019Assignee: Invensas CorporationInventors: Min Tao, Hoki Kim, Ashok S. Prabhu, Zhuowen Sun, Wael Zohni, Belgacem Haba
-
Patent number: 10325877Abstract: In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.Type: GrantFiled: April 23, 2018Date of Patent: June 18, 2019Assignee: Invensas CorporationInventors: Javier A. Delacruz, Abiola Awujoola, Ashok S. Prabhu, Christopher W. Lattin, Zhuowen Sun
-
Publication number: 20190096861Abstract: Apparatuses and methods relating generally to a microelectronic package for wafer-level chip scale packaging with fan-out are disclosed. In an apparatus, there is a substrate having an upper surface and a lower surface opposite the upper surface. A microelectronic device is coupled to the upper surface with the microelectronic device in a face-up orientation. Wire bond wires are coupled to and extending away from the upper surface. Posts of the microelectronic device extend away from a front face thereof. Conductive pads are formed in the substrate associated with the wire bond wires for electrical conductivity.Type: ApplicationFiled: November 27, 2018Publication date: March 28, 2019Applicant: Invensas CorporationInventors: Rajesh Katkar, Ashok S. Prabhu
-
Publication number: 20190027444Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.Type: ApplicationFiled: September 10, 2018Publication date: January 24, 2019Applicant: Invensas CorporationInventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
-
Patent number: 10181457Abstract: Apparatuses and methods relating generally to a microelectronic package for wafer-level chip scale packaging with fan-out are disclosed. In an apparatus, there is a substrate having an upper surface and a lower surface opposite the upper surface. A microelectronic device is coupled to the upper surface with the microelectronic device in a face-up orientation. Wire bond wires are coupled to and extending away from the upper surface. Posts of the microelectronic device extend away from a front face thereof. Conductive pads are formed in the substrate associated with the wire bond wires for electrical conductivity.Type: GrantFiled: October 24, 2016Date of Patent: January 15, 2019Assignee: Invensas CorporationInventors: Ashok S. Prabhu, Rajesh Katkar
-
Patent number: 10115678Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.Type: GrantFiled: November 6, 2017Date of Patent: October 30, 2018Assignee: Invensas CorporationInventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
-
Publication number: 20180240773Abstract: In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.Type: ApplicationFiled: April 23, 2018Publication date: August 23, 2018Applicant: Invensas CorporationInventors: Javier A. Delacruz, Abiola Awujoola, Ashok S. Prabhu, Christopher W. Lattin, Zhuowen Sun
-
Patent number: 10043779Abstract: Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device (“PoP”) with enhanced tolerance for warping. In one such packaged microelectronic device, interconnect structures are in an outer region of the packaged microelectronic device. A microelectronic device is coupled in an inner region of the packaged microelectronic device inside the outer region. A dielectric layer surrounds at least portions of shafts of the interconnect structures and along sides of the microelectronic device. The interconnect structures have first ends thereof protruding above an upper surface of the dielectric layer a distance to increase a warpage limit for a combination of at least the packaged microelectronic device and one other packaged microelectronic device directly coupled to protrusions of the interconnect structures.Type: GrantFiled: November 16, 2016Date of Patent: August 7, 2018Assignee: Invensas CorporationInventors: Ashok S. Prabhu, Rajesh Katkar
-
Patent number: 9991233Abstract: Package-on-package (“PoP”) devices with same level wafer-level packaged (“WLP”) components and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. The first conductive lines extend away from the upper surface of the package substrate. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines. WLP microelectronic components are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines.Type: GrantFiled: December 28, 2016Date of Patent: June 5, 2018Assignee: Invensas CorporationInventors: Min Tao, Hoki Kim, Ashok S. Prabhu, Zhuowen Sun, Wael Zohni, Belgacem Haba
-
Patent number: 9991235Abstract: Package-on-package (“PoP”) devices with upper RDLs of WLP (“WLP”) components and methods therefor are disclosed. In a PoP device, a first IC die is surface mount coupled to an upper surface of the package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with reference to the first IC. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located below a first RDL respectively thereof. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components.Type: GrantFiled: December 28, 2016Date of Patent: June 5, 2018Assignee: Invensas CorporationInventors: Min Tao, Hoki Kim, Ashok S. Prabhu, Zhuowen Sun, Wael Zohni, Belgacem Haba
-
Patent number: 9984992Abstract: In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.Type: GrantFiled: January 18, 2016Date of Patent: May 29, 2018Assignee: Invensas CorporationInventors: Javier A. DeLaCruz, Abiola Awujoola, Ashok S. Prabhu, Christopher W. Lattin, Zhuowen Sun
-
Patent number: 9985007Abstract: Package-on-package (“PoP”) devices with multiple levels and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. First and second conductive lines are coupled to the upper surface of the package substrate respectively at different heights in a fan-out region. A first molding layer is formed over the upper surface of the package substrate. A first and a second wafer-level packaged microelectronic component are located above an upper surface of the first molding layer respectively surface mount coupled to a first and a second set of upper portions of the first conductive lines. A third and a fourth wafer-level packaged microelectronic component are located above the first and the second wafer-level packaged microelectronic component respectively surface mount coupled to a first and a second set of upper portions of the second conductive lines.Type: GrantFiled: December 28, 2016Date of Patent: May 29, 2018Assignee: Invensas CorporationInventors: Min Tao, Hoki Kim, Ashok S. Prabhu, Zhuowen Sun, Wael Zohni, Belgacem Haba
-
Patent number: 9972573Abstract: Wafer-level packaged components are disclosed. In a wafer-level-packaged, an integrated circuit die has first contacts in an inner third region of a surface of the integrated circuit die. A redistribution layer has second contacts in an inner third region of a first surface of the redistribution layer and third contacts in an outer third region of a second surface of the redistribution layer opposite the first surface thereof. The second contacts of the redistribution layer are coupled for electrical conductivity to the first contacts of the integrated circuit die with the surface of the integrated circuit die face-to-face with the first surface of the redistribution layer. The third contacts are offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the redistribution layer, the third contacts being surface mount contacts.Type: GrantFiled: December 28, 2016Date of Patent: May 15, 2018Assignee: Invensas CorporationInventors: Min Tao, Hoki Kim, Ashok S. Prabhu, Zhuowen Sun, Wael Zohni, Belgacem Haba