Abstract: An assembly includes a plurality of stacked encapsulated microelectronic packages, each package including a microelectronic element having a front surface with a plurality of chip contacts at the front surface and edge surfaces extending away from the front surface. An encapsulation region of each package contacts at least one edge surface and extends away therefrom to a remote surface of the package. The package contacts of each package are disposed at a single one of the remote surfaces, the package contacts facing and coupled with corresponding contacts at a surface of a substrate nonparallel with the front surfaces of the microelectronic elements therein.

Abstract: A microelectronic assembly includes a stack of semiconductor chips each having a front surface defining a respective plane of a plurality of planes. A chip terminal may extend from a contact at a front surface of each chip in a direction towards the edge surface of the respective chip. The chip stack is mounted to substrate at an angle such that edge surfaces of the chips face a major surface of the substrate that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. An electrically conductive material electrically connects the chip terminals with corresponding substrate contacts.

Abstract: A microelectronic assembly includes a stack of microelectronic elements, e.g., semiconductor chips, each having a front surface defining a respective plane of a plurality of planes. A leadframe interconnect joined to a contact at a front surface of each chip may extend to a position beyond the edge surface of the respective microelectronic element. The chip stack is mounted to support element at an angle such that edge surfaces of the chips face a major surface of the support element that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. The leadframe interconnects are electrically coupled at ends thereof to corresponding contacts at a surface of the support element.

Abstract: An apparatus, and methods therefor, relates generally to an integrated circuit package. In such an apparatus, a platform substrate has a copper pad. An integrated circuit die is coupled to the platform substrate. A wire bond wire couples a contact of the integrated circuit die and the copper pad. A first end of the wire bond wire is ball bonded with a ball bond for direct contact with an upper surface of the copper pad. A second end of the wire bond wire is stitch bonded with a stitch bond to the contact.

Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Abstract: An assembly includes a plurality of stacked encapsulated microelectronic packages, each package including a microelectronic element having a front surface with a plurality of chip contacts at the front surface and edge surfaces extending away from the front surface. An encapsulation region of each package contacts at least one edge surface and extends away therefrom to a remote surface of the package. The package contacts of each package are disposed at a single one of the remote surfaces, the package contacts facing and coupled with corresponding contacts at a surface of a substrate nonparallel with the front surfaces of the microelectronic elements therein.

Abstract: Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

Abstract: An inductor device having an improved galvanic isolation layer arranged between a pair of coil and methods of its construction are described.

Abstract: An inductor device having an improved galvanic isolation layer arranged between a pair of coil and methods of its construction are described.

Abstract: Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

Abstract: In a method aspect, a multiplicity of ICs are attached to routing on a structurally supportive carrier (such as a wafer). The dice are encapsulated and then both the dice and the encapsulant layer are thinned with the carrier in place. A second routing layer is formed over the first encapsulant layer and conductive vias are provided to electrically couple the first and second routing layers as desired. External I/O contacts (e.g. solder bumps) are provided to facilitate electrical connection of the second routing layer (or a subsequent routing layer in stacked packages) to external devices. A contact encapsulant layer is then formed over the first encapsulant layer and the second routing layer in a manner that embeds the external I/O contacts at least partially therein. After the contact encapsulant layer has been formed, the carrier itself may be thinned significantly and singulated to provide a number of very low profile packages. The described approach can also be used to form stacked multi-chip packages.

Abstract: An integrated circuit package configured to incorporate a lead frame and methods for its making are is described. The package comprising an IC with aluminum bond pads in communication with circuitry of the die with lead frame with silver bond pads. The package having gold bumps bonded between the aluminum bond pad of the die and the silver bond pad of the lead frame. The package including an encapsulant envelope and including various materials and bond pad structures and constructed in a manner formed by thermosonically or thermocompressionally bonding the gold balls to the bond pads. Also, disclosed are methods of making the package.

Abstract: Methods and arrangements are described for forming an array of contacts for use in packaging one or more integrated circuit devices. In particular, various methods are described for forming contacts having thicknesses less than approximately 10 ?m, and in particular embodiments, between 0.5 to 2 ?m.

Abstract: An improved method and apparatus for packaging integrated circuits are described. More particularly, a method and apparatus for use in securing a plurality of integrated circuit dice to a lead frame panel are described. Each integrated circuit die includes an active surface having a multiplicity of solder bumps. The lead frame panel includes an array of device areas, each including a plurality of leads. The method includes positioning a plurality of dice into designated positions on a carrier such that the active surfaces of the dice are facing upwards. The carrier includes a carrier frame including an associated array of carrier device areas. A lead frame panel may be positioned over the carrier such that the solder bumps on the active surfaces of the dice are adjacent and in contact with the associated leads of the associated device areas.

Abstract: Aspects of the invention recite wire bonding on thinned portions of a lead-frame that is configured for use in an IC package. A harder lead-frame material, improved adhesive tape, and various structural features of the lead-frame itself, in various combinations or subcombinations, facilitate the attachment of wire bonds to thinned areas of the lead-frame. This eliminates the need for supports placed directly under the bond sites, removing unwanted conductive areas on the outer surface of an IC package.

Abstract: A method of fabricating a micro-array IC package is recited. A wafer has a B-stageable adhesive applied, and the wafer is diced. The individual dice are applied to a lead-frame via their adhesive, and wirebonded to associated leads. The lead-frame is then encapsulated, and solder connectors are applied. The lead-frame is then singulated to produce a plurality of lead-frame based micro-array packages. The process thus allows lead-frame based manufacturing methods to be employed in the production of BGA-type packages, allowing such packages to be produced faster and more efficiently.

Abstract: A lead-frame based substrate panel for use in semiconductor packaging is described. The substrate panel includes a lead-frame panel having at least one array of device areas. Each device area has a plurality of contacts. The lead-frame panel is filled with a dielectric material to form a relatively rigid substrate panel that can be used for packaging integrated circuits. The top surface of the dielectric material is typically substantially coplanar with the top surface of the lead-frame panel, and the bottom surface of the dielectric material is typically substantially coplanar with the bottom surface of the lead-frame panel.

Abstract: A solder pad configuration for use in an IC package is described. Various embodiments of the invention describe IC packages, lead-frames, or substrate panels configured with generally noncircular solder pads at their bottom surfaces. The noncircular shapes allow for greater surface area than circular solder pads having diameters equal to a major dimension of the noncircular shapes, while maintaining the same metal-to-metal clearance between the pads and adjacent leads. This increased surface area provides for stronger and more reliable solder joints.

Abstract: A die attach region for use in an IC package is described. The die attach region employs a number of posts interconnected with a number of support risers to provide a structure that upholds a semiconductor die while facilitating flow of an encapsulant material underneath the die during encapsulation. The posts and risers can be arranged in a number of configurations that each facilitate flow of encapsulant material. This die attach region can be incorporated into a lead-frame structure or a substrate panel for ease and efficiency of manufacture.

Abstract: A method for providing passive circuit functions in a multi-chip module and the multi-chip modules that result from incorporating these function is disclosed. Passive components such as resistors, capacitors and inductors are fabricated on or within a non-conductive spacer. The spacer is then placed between two active semiconductor dies and coupled electrically to either one or both of the dies. In this manner, area of the active dies that would normally have to be used for such passive components is freed for other uses and the spacer, which was already required in multi-chip modules, is endowed with extra functionality. In another embodiment, one or both surfaces of the spacer are coated with a conductive metal and the passive components are located within the spacer. In this embodiment, the spacer provides electromagnetic interference protection between the active dies.