Patents by Inventor Ashoke Ravi
Ashoke Ravi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12603670Abstract: A wireless communication device includes an antenna array with multiple antenna elements, an array of power amplifiers, and an array of phase shifters. Each antenna element is coupled to a power amplifier and a phase shifter. The device also includes transmitter circuitry coupled to the antenna array to encode a constant amplitude signal, which includes a power amplifier enable code to indicate which power amplifiers are to run in a subsequent data sample and a beam direction code to control beam direction of each phase shifter of the array of phase shifters in the subsequent data sample. The constant amplitude signal is then provided to the array of antenna elements and amplitude and phase modulation is combined over an air interface into a composite modulated signal.Type: GrantFiled: December 23, 2021Date of Patent: April 14, 2026Assignee: Intel CorporationInventors: Benjamin Jann, Ashoke Ravi, Paolo Madoglio
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Patent number: 12562745Abstract: For example, an apparatus may include a digitally-controlled frequency multiplier, which may be controllable according to a digital control input, to generate an output frequency signal having an output frequency, for example, by multiplying an input frequency of an input frequency signal. For example, the digitally-controlled frequency multiplier may include a phase generator configured to generate a plurality of phase-shifted signal groups corresponding to a respective plurality of first phase-shifts applied to the input frequency signal, a plurality of digital clock multipliers controllable according to the digital control input to generate a respective plurality of frequency-multiplied signals based on the plurality of phase-shifted signal groups, and a combiner to generate the output frequency signal based on a combination of the plurality of frequency-multiplied signals.Type: GrantFiled: June 16, 2022Date of Patent: February 24, 2026Assignee: INTEL CORPORATIONInventors: Ali Azam, Ashoke Ravi, Ofir Degani
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Patent number: 12556216Abstract: In various aspects, a radio frequency circuit is provided. The radio frequency circuit may include a substrate that may include a radio frequency front-end to antenna (RF FE-to-Ant) connector. The RF FE-to-Ant connector may include a conductor track structure and a substrate connection structure coupled to the conductor track structure. The substrate may include radio frequency front-end circuitry monolithically integrated in the substrate. The substrate connection structure may include at least one of a solderable structure, a weldable structure, or an adherable structure. The substrate connection structure may be configured to form at least one radio frequency signal interface with an antenna circuit connection structure of a substrate-external antenna circuit. The substrate may include an edge region. The substrate connection structure may be disposed in the edge region.Type: GrantFiled: November 3, 2020Date of Patent: February 17, 2026Assignee: INTEL CORPORATIONInventors: Jayprakash Thakur, Ofir Degani, Ronen Kronfeld, Ehud Reshef, Seong-Youp J. Suh, Tal Shoshana, Eytan Mann, Maruti Tamrakar, Ashoke Ravi, Jose Rodrigo Camacho Perez, Timo Sakari Huusari, Eli Borokhovich, Amir Rubin, Ofer Benjamin, Tae Young Yang, Harry Skinner, Kwan Ho Lee, Jaejin Lee, Dong-Ho Han, Shahar Gross, Eran Segev, Telesphor Kamgaing
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Patent number: 12556220Abstract: A tunable bandpass low-noise amplifier (LNA). The LNA includes a plurality of N-path filters and a plurality of cascode amplifiers. The cascode amplifiers are configured to amplify an input signal. Each N-path filter is coupled to a different one of the plurality of cascode amplifiers. The plurality of N-path filters are driven by local oscillator (LO) signals having different frequencies, and output nodes of the plurality of cascode amplifiers are coupled in parallel. The frequencies of the LO signals may be symmetrically spaced around a desired frequency (fLO). Each N-path filter may be coupled to a source of the common-gate device of the coupled cascode amplifier. The LO signals may be generated by a digital-to-time converter (DTC)-based frequency synthesizer. The frequencies of the LO signals supplied to the N-path filters may be adjusted to tune the bandwidth of the bandpass LNA.Type: GrantFiled: August 12, 2022Date of Patent: February 17, 2026Assignee: Intel CorporationInventors: Sashank Krishnamurthy, Ofir Degani, Ashoke Ravi
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Patent number: 12531583Abstract: For example, a transmitter, e.g., for a wireless communication device, may be configured to transmit a wideband Radio Frequency (RF) Transmit (Tx) signal having a wide bandwidth of at least 80 Megahertz (MHz). For example, the transmitter may be configured to generate the wideband RF Tx signal having the wide bandwidth based on a baseband signal. The transmitter may be configured to generate the wideband RF Tx signal including a suppressed third harmonic and a suppressed fifth harmonic.Type: GrantFiled: March 31, 2022Date of Patent: January 20, 2026Assignee: INTEL CORPORATIONInventors: Elan Banin, Assaf Ben-Bassat, Ashoke Ravi, Rotem Banin, Ofir Degani
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Publication number: 20250385701Abstract: Disclosed herein are devices, systems, and methods for applying a post-distortion scheme to recover a desired signal from a received signal. The device includes processing circuitry connected to storage, where the processing circuitry causes one or more antennas to simultaneously transmit a transmitted signal and receive a received signal, wherein the received signal comprises a desired signal to be recovered from the received signal. The processing circuitry also causes a gain block to amplify the received signal and a leaked portion of the transmitted signal into an amplified composite signal. The processing circuitry also determines a distortion of the gain block on the received signal based on the transmitted signal. The processing circuitry also applies to the amplified composite signal an inversion of the distortion to recover the desired signal from the received signal.Type: ApplicationFiled: June 14, 2024Publication date: December 18, 2025Inventors: Elan BANIN, Oren Ezra AVRAHAM, Ofir DEGANI, Sashank KRISHNAMURTHY, Ashoke RAVI
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Patent number: 12438284Abstract: For example, an apparatus may include a baseband controller configured to control a plurality of dual-polarization Radio Heads (RHs) to communicate a Multiple-Input-Multiple-Output (MIMO) transmission, the baseband controller configured to control a first dual-polarization RH of the plurality of dual-polarization RHs to communicate a first spatial stream of the MIMO transmission with a horizontal-polarization via one or more first dual-polarization antenna elements of the first dual-polarization RH, and to control a second dual-polarization RH of the plurality of dual-polarization RHs to communicate a second spatial stream of the MIMO transmission with a vertical-polarization via one or more second dual-polarization antenna elements of the second dual-polarization RH.Type: GrantFiled: June 23, 2021Date of Patent: October 7, 2025Assignee: INTEL CORPORATIONInventors: Ronen Kronfeld, Ofir Degani, Ashoke Ravi
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Patent number: 12431944Abstract: A circuit for suppressing undesired sub-harmonics includes a plurality of mixers, wherein the plurality of mixers are connected in parallel; a plurality of local oscillator signals (LO), wherein each of the plurality of LOs is associated with one of the plurality of mixers; an input to receive a plurality of phases of a driving clock, wherein each of the plurality of phases is a sub-harmonic of the driving clock, and wherein each phase of the driving clock is distributed to one of the plurality of mixers; wherein the plurality of mixers are configured to suppress one or more of the plurality of phases of the driving clock and amplify a desired phase of the driving clock.Type: GrantFiled: December 27, 2019Date of Patent: September 30, 2025Assignee: Intel CorporationInventors: Sanket Jain, Benjamin Jann, Ashoke Ravi, Satwik Patnaik
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Publication number: 20250219596Abstract: Embodiments may comprise low noise amplifier (LNA) circuitry with a tunable wideband and high linearity. Embodiments may increase the linearity of the LNA circuitry and reduce noise. The LNA circuitry may comprise an inverter having a differential input coupled with the antenna, a first cascode circuitry coupled between a differential output of the inverter and a second cascode stage circuitry, wherein the second cascode stage circuitry comprises a first N-path filter circuitry coupled with a first set of outputs of clock circuitry having a clock frequency of an incoming signal minus a delta frequency and a second N-path filter circuitry coupled with a second set of outputs of clock circuitry having a clock frequency of an incoming signal plus a delta frequency. Combining the response of the two N-path filter circuitries at plus and minus delta frequency may achieve frequency selectivity and attenuate blockers.Type: ApplicationFiled: December 29, 2023Publication date: July 3, 2025Inventors: Ashoke Ravi, Sashank Krishnamurthy, Soumya Gupta, Oren Ezra Avraham, Ofir Degani
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Patent number: 12316022Abstract: A phased array may include a clock stage configured to generate shifted clock signals. Each shifted clock signal may include a different phase. The phased array may also include a beamforming stage configured to generate a beamformed signal that includes a beam formed in a direction based on summed signals. In addition, the phased array may include slices. Each slice may include a filter stage and a feedback stage. The filter stage may be configured to generate a corresponding summed signal by filtering a portion of blocker and noise interference in a corresponding receive signal based on blocking signals and the shifted clock signals. The feedback stage may be configured to generate the blocking signals based on the shifted clock signals and the corresponding summed signal. The blocking signals may be representative of the blocker and noise interference in the corresponding receive signal.Type: GrantFiled: June 21, 2021Date of Patent: May 27, 2025Assignee: Intel CorporationInventors: Benjamin Jann, Ashoke Ravi
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Publication number: 20250112603Abstract: An amplifier structure may include a first amplifier substructure having a first amplifier and a first filter structure and provide a first high frequency output signal and a first low frequency output signal having a frequency lower than a frequency of the first high frequency output signal. It may include a second amplifier substructure having a second amplifier and a second filter structure and provide a second high frequency output signal and a second low frequency output signal having a frequency lower than the frequency of the second high frequency output signal. It may include a first combination node configured to receive the first high frequency output signal and the second low frequency output signal and to provide a first amplified signal, and a second combination node configured to receive the first low frequency output signal and the second high frequency output signal and to provide a second amplified signal.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Ashoke RAVI, Ofir DEGANI, Sashank KRISHNAMURTHY, Soumya GUPTA
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Publication number: 20250105864Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.Type: ApplicationFiled: December 6, 2024Publication date: March 27, 2025Inventors: Ashoke Ravi, Benjamin Jann, Satwik Patnaik, Elan Banin, Ofir Degani, Alexandros Margomenos, Igal Kushnir
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Patent number: 12255653Abstract: A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.Type: GrantFiled: June 24, 2021Date of Patent: March 18, 2025Assignee: Intel CorporationInventors: Ali Azam, Ashoke Ravi, Benjamin Jann
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Patent number: 12237589Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.Type: GrantFiled: May 2, 2022Date of Patent: February 25, 2025Assignee: Intel CorporationInventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
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Patent number: 12218426Abstract: An antenna module and communication device containing the antenna module are disclosed. The antenna module is disposed in a metal cavity. The antenna module includes a switched beam mm-wave antenna array having radiating elements separated by less than a wavelength of the radiating elements. The array is fed by a single transceiver chain. The array is disposed at the focal length of a low-profile mm-wave lens configured to steer the beam. A sub-10 GHz antenna is disposed closer to the opening of the cavity than the lens. The lens is a Fresnel Zone Plate lens having a focal length of less than about the wavelength of the beam, or a Saucer lens having shells of different refractive indexes and having a profile that is more than 6 times smaller than a Luneburg lens with a same focal length.Type: GrantFiled: December 10, 2020Date of Patent: February 4, 2025Assignee: Intel CorporationInventors: Tae Young Yang, Seong-Youp John Suh, Harry G. Skinner, Ashoke Ravi, Ofir Degani, Ronen Kronfeld
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Patent number: 12191897Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.Type: GrantFiled: January 2, 2024Date of Patent: January 7, 2025Assignee: Intel CorporationInventors: Ashoke Ravi, Benjamin Jann, Satwik Patnaik
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Patent number: 12149207Abstract: Techniques are disclosed to allow for a switched capacitor digital power amplifier (PA) that operates using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg.Type: GrantFiled: May 18, 2021Date of Patent: November 19, 2024Assignee: Intel CorporationInventors: Ofir Degani, Assaf Ben-Bassat, Ashoke Ravi, Ina Shternberg, Naor Shay
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Patent number: 12078747Abstract: A method and apparatus for generating a frequency-modulated continuous wave (FMCW) signal. The apparatus may include a first oscillator configured to generate a first oscillation signal, a frequency modulator configured to generate a frequency-modulated oscillation signal from the first oscillation signal based on a sequence of control words, a frequency modulation code generator configured to generate a sequence of frequency modulation codes for generating an FMCW waveform, and a frequency multiplier configured to generate the FMCW signal by up-converting the frequency-modulated oscillation signal. The sequence of control words is generated based on the sequence of frequency modulation codes. The apparatus may include a second oscillator configured to generate a second oscillation signal, and a phase detector configured to detect a phase difference between the first oscillation signal and the second oscillation signal and generate an offset code based on the phase difference.Type: GrantFiled: March 12, 2019Date of Patent: September 3, 2024Assignee: Apple Inc.Inventors: Igal Kushnir, Elan Banin, Rotem Banin, Ofir Degani, Ashoke Ravi
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Publication number: 20240243477Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.Type: ApplicationFiled: February 15, 2024Publication date: July 18, 2024Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Marian Verhelst, Yossi Tsfati, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
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Publication number: 20240223416Abstract: A system includes a processor configured to determine a frequency offset between a first local oscillator and a second local oscillator using a combined radio signal received at a first transceiver circuit; wherein the combined radio signal comprises a first signal transmitted by the first transceiver circuit and a second signal transmitted by a second transceiver circuit.Type: ApplicationFiled: December 29, 2022Publication date: July 4, 2024Inventors: Hossein ALAVI, Elan BANIN, Ofir DEGANI, Ashoke RAVI
