Patents by Inventor Ashoke Ravi

Ashoke Ravi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and a system for calibrating a phase nonlinearity of a digital-to-time converter
    Patent number: 11245403
    Abstract: A method for calibrating a phase nonlinearity of a digital-to-time converter is provided. The method includes generating, based on a control word, a reference signal using a phase-locked loop. A frequency of the reference signal is equal to a frequency of an output signal of the digital-to-time converter. Further, the method includes measuring a temporal order of a transition of the output signal from a first signal level to a second signal level, and a transition of the reference signal from the first signal level to the second signal level. The method additionally includes adjusting a first entry of a look-up table based on the measured temporal order.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: February 8, 2022
    Assignee: INTEL CORPORATION
    Inventors: Sebastian Sievert, Ofir Degani, Ashoke Ravi
  • RADIO DESIGN, CONTROL, AND ARCHITECTURE
    Publication number: 20210391853
    Abstract: Techniques are described related to digital radio control, partitioning, and operation. The various techniques described herein enable high-frequency local oscillator signal generation and frequency multiplication using radio-frequency (RF) digital to analog converters (RFDACs). The use of these components and others described throughout this disclosure allow for the realization of various improvements. For example, digital, analog, and hybrid beamforming control are implemented and the newly-enabled digital radio architecture partitioning enables radio components to be pushed to the radio head, allowing for the omission of high frequency cables and/or connectors.
    Type: Application
    Filed: December 28, 2018
    Publication date: December 16, 2021
    Inventors: Benjamin Jann, Ashoke Ravi, Satwik Patnaik, Elan Banin, Ofir Degani, Nebil Tanzi, Brandon Davis, Igal Kushnir, Jonathan Jensen, Sidharth Dalmia, Peter Pawliuk
  • DIGITAL RADIO HEAD CONTROL
    Publication number: 20210367629
    Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.
    Type: Application
    Filed: August 4, 2021
    Publication date: November 25, 2021
    Inventors: Ashoke Ravi, Benjamin Jann, Satwik Patnaik, Alexandros Margomenos, Igal Kushnir, Elan Banin, Ofir Degani
  • Noise reduction and spur and distortion cancellation techniques
    Patent number: 11146276
    Abstract: A wireless communication device can include an antenna configured to sense a radio frequency (RF) signal. The wireless communication device can include signal estimation circuitry configured to generate estimates of amplitude and frequency for unmodulated spurs within the RF signal. The wireless communication device can further include multi-tone generator circuitry coupled to the signal estimation circuitry and configured to generate a composite spur cancellation signal based on the estimates of amplitude and frequency for unmodulated spurs within the RF signal. The wireless communication device can further include adder circuitry configured to subtract the spur cancellation signal from the RF signal to generate a spur cancelled signal.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Niranjan Karandikar, Mohammed Alam, Gregory Chance, Armando Cova, Michael Milyard, John J. Parkes, Jr., Ashoke Ravi, Daniel Schwartz, Dong-Jun Yang
  • Digital radio head control
    Patent number: 11121731
    Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: September 14, 2021
    Assignee: Intel Corporation
    Inventors: Ashoke Ravi, Benjamin Jann, Satwik Patnaik, Elan Banin, Igal Kushnir, Ofir Degani, Alexandros Margomenos
  • Transceiver with inseparable modulator demodulator circuits
    Patent number: 11095427
    Abstract: A transceiver, including a modulation circuit configured to modulate a first digital word into a first modulated time signal; and a demodulation circuit configured to demodulate a second modulated time signal into a second digital word, wherein the modulation and demodulation circuits are operable without an external clock source, and inseparably share one or more same circuit elements. Also, a tunable delay line may be configured to set a time rate of the modulation, wherein the modulation circuit and the demodulation circuit inseparably share the tunable delay line.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Rotem Banin, Elan Banin, Ofir Degani, Ronen Gernizky, Ashoke Ravi
  • A METHOD AND A SYSTEM FOR CALIBRATING A PHASE NONLINEARITY OF A DIGITAL-TO-TIME CONVERTER
    Publication number: 20210143823
    Abstract: A method for calibrating a phase nonlinearity of a digital-to-time converter is provided. The method includes generating, based on a control word, a reference signal using a phase-locked loop. A frequency of the reference signal is equal to a frequency of an output signal of the digital-to-time converter. Further, the method includes measuring a temporal order of a transition of the output signal from a first signal level to a second signal level, and a transition of the reference signal from the first signal level to the second signal level. The method additionally includes adjusting a first entry of a look-up table based on the measured temporal order.
    Type: Application
    Filed: July 17, 2017
    Publication date: May 13, 2021
    Inventors: Sebastian SIEVERT, Ofir DEGANI, Ashoke RAVI
  • NOISE REDUCTION AND SPUR AND DISTORTION CANCELLATION TECHNIQUES
    Publication number: 20210067163
    Abstract: A wireless communication device can include an antenna configured to sense a radio frequency (RF) signal. The wireless communication device can include signal estimation circuitry configured to generate estimates of amplitude and frequency for unmodulated spurs within the RF signal. The wireless communication device can further include multi-tone generator circuitry coupled to the signal estimation circuitry and configured to generate a composite spur cancellation signal based on the estimates of amplitude and frequency for unmodulated spurs within the RF signal. The wireless communication device can further include adder circuitry configured to subtract the spur cancellation signal from the RF signal to generate a spur cancelled signal.
    Type: Application
    Filed: March 30, 2018
    Publication date: March 4, 2021
    Inventors: Niranjan Karandikar, Mohammed Alam, Gregory Chance, Armando Cova, Michael Milyard, John J. Parkes, JR., Ashoke Ravi, Daniel Schwartz, Dong-Jun Yang
  • DIGITAL RADIO HEAD CONTROL
    Publication number: 20210067182
    Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 4, 2021
    Inventors: Ashoke Ravi, Jann Benjamin, Satwik Patnaik, Elan Banin, Igal Kushnir, Ofir Degani, Alexandros Margomenos
  • Methods and apparatus for wideband and fast chirp generation for radar systems
    Patent number: 10911274
    Abstract: Methods, apparatus, systems and articles of manufacture for wideband and fast chirp generation for radar systems are disclosed herein. An example apparatus includes a phase digital-to-analog converter to convert a digital input that specifies at least one of a phase modulation or a frequency modulation into an analog output, and to generate a phase modulated output centered on an intermediate frequency. The example apparatus also includes a frequency multiplier to frequency multiply the phase modulated output centered on the intermediate frequency by a multiplication factor to generate a chirp signal.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Kailash Chandrashekar, Ashoke Ravi
  • Multiplying delay lock loop (MDLL) and method of averaging ring oscillator signals for jitter compensation
    Patent number: 10840916
    Abstract: Aspects of present disclosure of multiplying delay lock loop (MDLL) circuitry and communication devices are generally described herein. The MDLL circuitry may comprise a multiplexer and a ring oscillator. The ring oscillator may comprise a cascade of delay elements. The multiplexer may receive a reference clock signal and may receive a ring oscillator output signal from a final delay element of the cascade of delay elements. The multiplexer may select, as a ring oscillator input signal, either the reference clock signal or the ring oscillator output signal. The ring oscillator may determine a jitter estimate based at least partly on a comparison between output signals of two particular delay elements of the cascade. The ring oscillator may compensate delay responses of the delay elements of the cascade based at least partly on the jitter estimate.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: Ashoke Ravi, Ofir Degani
  • Apparatus, system and method of generating a frequency output with a digitally controlled ring oscillator (DCRO)
    Patent number: 10840923
    Abstract: For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the plurality of stages comprising a plurality of inverter modules controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of second stages in the plurality of stages; a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 17, 2020
    Assignee: INTEL IP CORPORATION
    Inventors: Ashoke Ravi, Rotem Banin, Ofir Degani, David Ben-Haim, Yigal Kalmanovich
  • Switched capacitor radio frequency digital power amplifier and radio frequency digital-to-analog converter
    Publication number: 20200321924
    Abstract: A switched capacitor digital power amplifier (DPA) or a digital-to-analog converter (DAC) is disclosed. The DPA/DAC includes a plurality of switched capacitor cells connected in parallel. Each switched capacitor cell includes a capacitor and a switch. The switch selectively drives the capacitor in response to an input digital codeword. The switched capacitor cells are divided into sub-arrays and a series capacitor is inserted in series between two adjacent sub-arrays of switched capacitor cells. All the sub-arrays of switched capacitor cells may be in a unary-coded structure. Alternatively, at least one of the sub-arrays may be in a C-2C structure and at least one another sub-array may be in a unary-coded structure. The switch in the switched capacitor cells is driven by a local oscillator signal, and a phase correction buffer may be added for adjusting a delay of the local oscillator signal supplied to sub-arrays of switched capacitor cells.
    Type: Application
    Filed: December 29, 2017
    Publication date: October 8, 2020
    Inventors: Ali AZAM, Ashoke RAVI, Bassam KHAMAISI, Ofir DEGANI
  • MULTIPLYING DELAY LOCK LOOP (MDLL) AND METHOD OF AVERAGING RING OSCILLATOR SIGNALS FOR JITTER COMPENSATION
    Publication number: 20200228122
    Abstract: Aspects of present disclosure of multiplying delay lock loop (MDLL) circuitry and communication devices are generally described herein. The MDLL circuitry may comprise a multiplexer and a ring oscillator. The ring oscillator may comprise a cascade of delay elements. The multiplexer may receive a reference clock signal and may receive a ring oscillator output signal from a final delay element of the cascade of delay elements. The multiplexer may select, as a ring oscillator input signal, either the reference clock signal or the ring oscillator output signal. The ring oscillator may determine a jitter estimate based at least partly on a comparison between output signals of two particular delay elements of the cascade. The ring oscillator may compensate delay responses of the delay elements of the cascade based at least partly on the jitter estimate.
    Type: Application
    Filed: August 7, 2017
    Publication date: July 16, 2020
    Inventors: Ashoke Ravi, Ofir Degani
  • Digital phase locked loop frequency estimation
    Patent number: 10680619
    Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a controlled oscillator signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: June 9, 2020
    Assignee: Intel IP Corporation
    Inventors: Elan Banin, Roy Amel, Ran Shimon, Ashoke Ravi, Nati Dinur
  • Systems and methods for frequency domain calibration and characterization
    Patent number: 10630299
    Abstract: A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: April 21, 2020
    Assignee: Apple Inc.
    Inventors: Cho-Ying Lu, William Yee Li, Khoa Minh Nguyen, Ashoke Ravi, Maneesha Yellepeddi, Binta M. Patel
  • WIRELESS COMMUNICATION TECHNOLOGY, APPARATUSES, AND METHODS
    Publication number: 20200091608
    Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.
    Type: Application
    Filed: December 20, 2017
    Publication date: March 19, 2020
    Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
  • METHODS AND APPARATUS FOR WIDEBAND AND FAST CHIRP GENERATION FOR RADAR SYSTEMS
    Publication number: 20200028722
    Abstract: Methods, apparatus, systems and articles of manufacture for wideband and fast chirp generation for radar systems are disclosed herein. An example apparatus includes a phase digital-to-analog converter to convert a digital input that specifies at least one of a phase modulation or a frequency modulation into an analog output, and to generate a phase modulated output centered on an intermediate frequency. The example apparatus also includes a frequency multiplier to frequency multiply the phase modulated output centered on the intermediate frequency by a multiplication factor to generate a chirp signal.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Inventors: Kailash Chandrashekar, Ashoke Ravi
  • SYSTEMS AND METHODS FOR FREQUENCY DOMAIN CALIBRATION AND CHARACTERIZATION
    Publication number: 20190393880
    Abstract: A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.
    Type: Application
    Filed: July 1, 2019
    Publication date: December 26, 2019
    Inventors: Cho-Ying Lu, William Yee Li, Khoa Minh Nguyen, Ashoke Ravi, Maneesha Yellepeddi, Binta M. Patel
  • Apparatus and a method for generating a radio frequency signal
    Patent number: 10516563
    Abstract: An apparatus for generating a radio frequency signal based on a symbol within a constellation diagram is provided. The constellation diagram is spanned by a first axis representing an in-phase component and an orthogonal second axis representing a quadrature component. The apparatus includes a processing unit configured to select a segment of a plurality of segments of the constellation diagram containing the symbol. The segment is delimited by a third axis and a fourth axis each crossing the origin of the constellation diagram and spanning an opening angle of the segment of less than about 90°. The processing unit is further configured to calculate a first coordinate of the symbol with respect to the third axis, and a second coordinate of the symbol with respect to the fourth axis. The apparatus further includes a plurality of digital-to-analog converter cells configured to generate the radio frequency signal using the first coordinate and the second coordinate.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 24, 2019
    Assignee: Intel IP Corporation
    Inventors: Sebastian Sievert, Ofir Degani, Ashoke Ravi, Rotem Banin