Patents by Inventor Ashwin Narasimha

Ashwin Narasimha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11769048
    Abstract: In an example embodiment, a single machine learned model that allows for ranking of entities across all of the different combinations of node types and edge types is provided. The solution calibrates the scores from Edge-FPR models to a single scale. Additionally, the solution may utilize a per-edge type multiplicative factor dictated by the true importance of an edge type, which is learned through a counterfactual experimentation process. The solution may additionally optimize on a single, common downstream metric, specifically downstream interactions that can be compared against each other across all combinations of node types and edge types.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: September 26, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Parag Agrawal, Ankan Saha, Yafei Wang, Yan Wang, Eric Lawrence, Ashwin Narasimha Murthy, Aastha Nigam, Bohong Zhao, Albert Lingfeng Cui, David Sung, Aastha Jain, Abdulla Mohammad Al-Qawasmeh
  • Patent number: 11640333
    Abstract: Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: May 2, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Vijay Karamcheti, Ashwin Narasimha
  • Patent number: 11599505
    Abstract: By way of example, a data storage system may comprise, a non-transitory storage device storing data blocks in chunks, and a storage logic coupled to the non-transitory storage device that manages storage of data on the storage device. The storage logic is executable to receive a data stream for storage in a non-transitory storage device, the data stream including one or more data blocks, analyze the data stream to determine a domain, retrieve a pre-configured reference set based on the domain, and deduplicate the one or more data blocks of the data stream using the pre-configured reference set.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: March 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Ashwin Narasimha, Vijay Karamcheti, Tanay Goel
  • Patent number: 11579973
    Abstract: The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 14, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Ashwin Narasimha, Kenneth Alan Okin
  • Patent number: 11366817
    Abstract: Technologies for scoring and ranking cohorts containing content items using a machine-learned model are provided. The disclosed techniques include a cross-cohort optimization system that stores, within memory, cohort definition criteria for each cohort of a plurality of cohorts. The optimization system, for a particular user, for each cohort, identifies a plurality of content items that belong to the specific cohort based upon the cohort definition criteria. Using a machine-learned model, the optimization system generates a score for the specific cohort with respect to the particular user's intentions. The optimization system generates a ranking for the plurality of cohorts based on the respective scores of each cohort. The optimization system causes the plurality of content items of each cohort to be displayed concurrently on a computing device of the particular user. Display order for the plurality of cohorts is based on the ranking determined for the plurality of cohorts.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: June 21, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Parag Agrawal, Aastha Jain, Yafei Wang, Ashwin Narasimha Murthy
  • Publication number: 20220083853
    Abstract: In an example embodiment, a single machine learned model that allows for ranking of entities across all of the different combinations of node types and edge types is provided. The solution calibrates the scores from Edge-FPR models to a single scale. Additionally, the solution may utilize a per-edge type multiplicative factor dictated by the true importance of an edge type, which is learned through a counterfactual experimentation process. The solution may additionally optimize on a single, common downstream metric, specifically downstream interactions that can be compared against each other across all combinations of node types and edge types.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 17, 2022
    Inventors: Parag Agrawal, Ankan Saha, Yafei Wang, Yan Wang, Eric Lawrence, Ashwin Narasimha Murthy, Aastha Nigam, Bohong Zhao, Albert Lingfeng Cui, David Sung, Aastha Jain, Abdulla Mohammad Al-Qawasmeh
  • Publication number: 20220035699
    Abstract: Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.
    Type: Application
    Filed: October 14, 2021
    Publication date: February 3, 2022
    Inventors: Ashish SINGHAI, Vijay KARAMCHETI, Ashwin NARASIMHA
  • Publication number: 20210390017
    Abstract: The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.
    Type: Application
    Filed: August 31, 2021
    Publication date: December 16, 2021
    Inventors: Ashish SINGHAI, Ashwin NARASIMHA, Kenneth Alan OKIN
  • Patent number: 11150984
    Abstract: Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: October 19, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Vijay Karamcheti, Ashwin Narasimha
  • Patent number: 11132255
    Abstract: The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: September 28, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Ashwin Narasimha, Kenneth Alan Okin
  • Publication number: 20210034635
    Abstract: Technologies for scoring and ranking cohorts containing content items using a machine-learned model are provided. The disclosed techniques include a cross-cohort optimization system that stores, within memory, cohort definition criteria for each cohort of a plurality of cohorts. The optimization system, for a particular user, for each cohort, identifies a plurality of content items that belong to the specific cohort based upon the cohort definition criteria. Using a machine-learned model, the optimization system generates a score for the specific cohort with respect to the particular user's intentions. The optimization system generates a ranking for the plurality of cohorts based on the respective scores of each cohort. The optimization system causes the plurality of content items of each cohort to be displayed concurrently on a computing device of the particular user. Display order for the plurality of cohorts is based on the ranking determined for the plurality of cohorts.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Parag Agrawal, Aastha Jain, Yafei Wang, Ashwin Narasimha Murthy
  • Patent number: 10809928
    Abstract: Various aspects for data deduplication in a storage system are provided. For instance, a storage controller may perform operations including receiving a data chunk including a set of data blocks, determining a signature for the data chunk, and comparing the signature and a set of reference signatures to determine a match. Responsive to a match, the operations may further include identifying a reference data chunk including a set of comparison blocks associated with the matched reference signature, performing a deduplication technique on the set of data blocks based on the set of comparison blocks, and identifying a subsequent reference data chunk for an estimated next data chunk based on identification of the reference data chunk and prior to receipt of the next data chunk.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: October 20, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ajith Kumar Battaje, Tanay Goel, Kiran Shivanagoudar, Saurabh Manchanda, Ashwin Narasimha, Ashish Singhai
  • Publication number: 20200218603
    Abstract: Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.
    Type: Application
    Filed: March 19, 2020
    Publication date: July 9, 2020
    Inventors: Ashish SINGHAI, Vijay KARAMCHETI, Ashwin NARASIMHA
  • Publication number: 20200218609
    Abstract: The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.
    Type: Application
    Filed: March 13, 2020
    Publication date: July 9, 2020
    Inventors: Ashish SINGHAI, Ashwin NARASIMHA, Kenneth Alan OKIN
  • Patent number: 10691531
    Abstract: Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: June 23, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Vijay Karamcheti, Ashwin Narasimha
  • Patent number: 10628260
    Abstract: The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: April 21, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Ashwin Narasimha, Kenneth Alan Okin
  • Patent number: 10565057
    Abstract: A data storage system comprises, a storage device having segments that are configured to store data, and storage logic coupled to the storage device that manages storage of data on the storage device using a translation table. The storage logic is executable to receive a first marker as part of a backup request, generate a second marker encapsulating a state of the storage device at a second time, calculate a difference between the first marker and the second marker, and generate a backup of data stored in the storage device based on the calculated difference between the first marker and the second marker. A garbage collection (GC) barrier may be set based on serial numbers associated with backup segments, and the garbage collection barrier may be incrementally released by releasing the garbage collection barrier for each segment after the segment has been backed up.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: February 18, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Vijay Karamcheti, Ashwin Narasimha
  • Patent number: 10552284
    Abstract: Techniques for controlling power on a PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method for controlling power including providing power to a memory attached via the PCIe interface; monitoring a state of the attached memory; determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold; and stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: February 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Krishanth Skandakumaran, Arun Kumar Medapati, Sri Rama Namala, Ashwin Narasimha, Ajith Kumar B
  • Patent number: 10475517
    Abstract: A sequence of contiguous pages in an erase block in a non-volatile memory device is programmed and erased. Next, all of the pages in the erase block are programmed with data. Then, the data is read back and verified to determine whether there is an error in the data. When there is an error in the data, then the last page in the sequence is identified as being unstable. If there is no error in the data, then the last page in that sequence is identified as being stable. Thus, the recorded information identifies a point of instability in the erase block. Instabilities can be stabilized by performing additional writes to fill the partially filled word line.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: November 12, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ajith Kumar Battaje, Mahesh Mandya Vardhamanaiah, Ashwin Narasimha, Sandeep Sharma
  • Patent number: 10275376
    Abstract: A method for implementing cross device redundancy schemes with a single commit by receiving, by a write page allocation unit, a request to allocate data grains; responsive to receiving the request, performing, by the write page allocation unit, an analysis of a predetermined data layout map associated with a grain memory to identify a memory segment; allocating, by the write page allocation unit, a number of data grains to the memory segment, while computing redundancy data associated with the number of data grains; storing the number of data grains and the redundancy data to the memory segment of the grain memory; determining, by the write page allocation unit, whether a storage threshold associated with the grain memory has been satisfied; and responsive to the storage threshold associated with the grain memory being satisfied, transmitting data grains and redundancy data stored in the memory segment to one or more storage devices.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: April 30, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ashwin Narasimha, Krishanth Skandakumaran, Vijay Karamcheti, Ashish Singhai