Abstract: A method of forming a buried resistor within a cavity for use in electronic packages using two glass impregnated dielectric layers, one with a clearance hole, the second with a resistor core, the clearance hole being placed over the resistor core and the assembly fusion bonded. The space remaining around the resistor core is filled with a soldermask material and the assembly is coated with metal. Thru-holes are drilled, cleaned, and plated and then the metal coating is etched and partially removed. The soldermask is then removed and a layer of gold plating is applied to the exposed metal surfaces. The use of glass impregnated dielectric layers and fusion bonding eliminates the fluorinated ethylene propylene resin (FEP) bleed problem associated with previous buried resistor cavity assemblies.

Abstract: A method of forming a buried resistor within a cavity for use in electronic packages using two glass impregnated dielectric layers, one with a clearance hole, the second with a resistor core, the clearance hole being placed over the resistor core and the assembly fusion bonded. The space remaining around the resistor core is filled with a soldermask material and the assembly is coated with metal. Thru-holes are drilled, cleaned, and plated and then the metal coating is etched and partially removed. The soldermask is then removed and a layer of gold plating is applied to the exposed metal surfaces. The use of glass impregnated dielectric layers and fusion bonding eliminates the fluorinated ethylene propylene resin (FEP) bleed problem associated with previous buried resistor cavity assemblies.

Abstract: A method of making a printed circuit board in which at least three substrates are aligned and bonded together (e.g., using lamination). Two of the substrates have openings formed therein, with each opening including a cover member located therein. During lamination, the cover members for a seal and prevent dielectric material (e.g., resin) liquefied during the lamination from contacting the conductive layers on the opposed surfaces of the inner (first) substrate. A PCB is thus formed with either a projecting edge portion or a plurality of cavities therein such that electrical connection may be made to the PCB using an edge connector or the like.

Abstract: A method of inspecting articles using an imaging inspection apparatus which utilizes a plurality of individual imaging devices for directing beams onto the articles having objects therein to detect the objects based on established criteria. The method involves the enhanced cooling of the heat-generating imaging devices in which a fan directs cooling fluid onto a plurality of deflectors which in turn direct said fluid onto selected ones of said imaging devices.

Abstract: A method of making an imaging inspection apparatus which involves positioning a plurality of individual imaging devices (e.g., X-ray Computer Tomography scanning devices) on a frame for directing beams onto articles having objects therein to detect the objects based on established criteria. The method also involves providing a cooling structure in such a manner that it will direct cooling fluid onto the imaging devices to cool these during apparatus operation.

Abstract: A method of inspecting articles using an imaging inspection apparatus which utilizes a plurality of individual imaging devices for directing beams onto the articles having objects therein to detect the objects based on established criteria. The method involves the enhanced cooling of the heat-generating imaging devices in which a fan directs cooling fluid onto a plurality of deflectors which in turn direct said fluid onto selected ones of said imaging devices.

Abstract: A method of making a printed circuit board in which at least three substrates are aligned and bonded together (e.g., using lamination). Two of the substrates have openings formed therein, with each opening including a cover member located therein. During lamination, the cover members for a seal and prevent dielectric material (e.g., resin) liquefied during the lamination from contacting the conductive layers on the opposed surfaces of the inner (first) substrate. A PCB is thus formed with either a projecting edge portion or a plurality of cavities therein such that electrical connection may be made to the PCB using an edge connector or the like.

Abstract: A method of making an imaging inspection apparatus which involves positioning a plurality of individual imaging devices (e.g., X-ray Computer Tomography scanning devices) on a frame for directing beams onto articles having objects therein to detect the objects based on established criteria. The method also involves providing a cooling structure in such a manner that it will direct cooling fluid onto the imaging devices to cool these during apparatus operation.

Abstract: An imaging inspection apparatus which utilizes a plurality of individual imaging devices (e.g., X-ray Computer Tomography scanning devices) positioned on a frame for directing beams onto articles having objects therein to detect the objects based on established criteria. The apparatus utilizes a cooling structure to provide cooling to the imaging devices.

Abstract: An imaging inspection apparatus which utilizes a plurality of individual imaging devices (e.g., X-ray Computer Tomography scanning devices) for directing beams onto articles having objects therein to detect the objects based on established criteria. The apparatus utilizes a cooling structure for directing cooling fluid (e.g., air) toward and over the devices, the structure including a fan for directing cooling fluid in a first direction and a plurality of fluid deflectors for deflecting at least part of the fluid toward respective ones of the devices.

Abstract: A hybrid photolithography process for printed circuit board patterning combines two types of photoresist applications to achieve superior protection of printed circuit board (PCB) ‘plated through holes’ (PTH). In a first step, electro-deposited (ED) photoresist (also known as “ED resist”) is applied to a fully copper plated PCB including the ‘plated through holes’ to protect the outer layers and the ‘plated through holes’ from copper etchant solution. In a second step, the electro-deposited photoresist is imaged (exposed) and patterned (developed). In a third step, after developing the circuit image, a layer of Dry Film resist is applied to the panel of the PCB on top of the developed electro-deposited (ED) photoresist. This Dry Film resist layer will ‘tent’ the plated through holes by adding an extra layer of protection to the plated through holes. In a fourth step, the dry film resist is then exposed and developed. At this point, the PCB is etched as normal and all subsequent processing remains unchanged.

Abstract: A hybrid photolithography process for printed circuit board patterning combines two types of photoresist applications to achieve superior protection of printed circuit board (PCB) ‘plated through holes’ (PTH). In a first step, electro-deposited (ED) photoresist (also known as “ED resist”) is applied to a fully copper plated PCB including the ‘plated through holes’ to protect the outer layers and the ‘plated through holes’ from copper etchant solution. In a second step, the electro-deposited photoresist is imaged (exposed) and patterned (developed). In a third step, after developing the circuit image, a layer of Dry Film resist is applied to the panel of the PCB on top of the developed electro-deposited (ED) photoresist. This Dry Film resist layer will ‘tent’ the plated through holes by adding an extra layer of protection to the plated through holes. In a fourth step, the dry film resist is then exposed and developed.

Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Abstract: An electronic package and method of making the electronic package is provided. An opening in the substrate of the electronic package is formed to substantially prevent adhesive which can bleed from under an electronic device from contacting conductive pads on the substrate. An electrical coupling is formed between the package's electronic device and conductive pads.

Abstract: A technique is provided for forming a circuitized substrate which substantially reduces defects in a circuit board formed of multiple layers of dielectric material on each of which layers electrical circuitry is formed. Each layer of dielectric material is formed of two distinct and separate coatings or sheets or films of a photopatternable dielectric material which is photoformed to provide through openings to the layer of circuitry below and then plated with the desired circuitry including plating in the photoformed openings to form vias. In this way if there is a pin hole type defect in either coating or sheet of dielectric material, in all probability it will not align with a similar defect in the other sheet or coating of the dielectric layer, thus preventing unwanted plating extending from one layer of circuitry to the underlying layer of circuitry.

Abstract: A technique is provided for forming a circuitized substrate which substantially reduces defects in a circuit board formed of multiple layers of dielectric material on each of which layers electrical circuitry is formed. Each layer of dielectric material is formed of two distinct and separate coatings or sheets or films of a photopatternable dielectric material which is photoformed to provide through openings to the layer of circuitry below and then plated with the desired circuitry including plating in the photoformed openings to form vias. In this way if there is a pin hole type defect in either coating or sheet of dielectric material, in all probability it will not align with a similar defect in the other sheet or coating of the dielectric layer, thus preventing unwanted plating extending from one layer of circuitry to the underlying layer of circuitry.

Abstract: A process for making a printed circuit board is provided. The process employs a noble metal as an etch mask for subtractive circuitization and as a seed layer for secondary finishing. In a preferred embodiment of the invention, a dielectric is covered by a conductive layer of metal such as copper, a patterned photoresist is applied, additional copper is deposited on areas not covered by the photoresist, and a palladium etch mask/seed layer is deposited on the copper. The palladium layer remains sufficiently active for deposition of nickel or gold on the circuitry for purposes such as wire bonding.

Abstract: A method for planarizing an exposed metal surface on a substrate is provided in which surface irregularities are eliminated. A photoresist layer is first removed from the substrate. Then a conformal planarizing head is placed in contact with the metal surface while chemical etchant essentially free of abrasives is supplied to an interface between the metal substrate and the planarizing head. The surface is then planarized until it is free of irregularties.