Abstract: A method of making a circuitized substrate wherein fill material is forced into the substrate's holes to thus provide additional support for conductive circuitry or the like thereon, thus increasing the final product's circuit density. The fill is provided in a substantially uncured state, following which partial cure occurs. Thereafter, the fill is substantially fully cured and the aforementioned circuit elements may then be provided directly thereon. Alternatively, a dual fill process is used with both quantities of uncured fill being disposed in each hole and then cured by a singular UV exposure step.

Abstract: Bridging between electrically conductive circuit features during conformal plating is prevented by avoiding the deposition of catalytic seed material onto non-circuit areas of the substrate. Preparatory to forming electrical circuit features on a nonconductive substrate by the full additive process, extraneous seed material is either trapped between two layers of a photoimageable film, whereby it is unavailable during plating, or deposited on the surface of an aqueous photoimageable film, which is removed prior to plating. The method embodying the present invention eliminates the need for seed removal after initial plating and prior to conformal plating of a precious metal over the initial plating.

Abstract: Bridging between electrically conductive circuit features during conformal plating is prevented by avoiding the deposition of catalytic seed material onto non-circuit areas of the substrate. Preparatory to forming electrical circuit features on a nonconductive substrate by the full additive process, extraneous seed material is either trapped between two layers of a photoimageable film, whereby it is unavailable during plating, or deposited on the surface of an aqueous photoimageable film, which is removed prior to plating. The method embodying the present invention eliminates the need for seed removal after initial plating and prior to conformal plating of a precious metal over the initial plating.

Abstract: A method of making a circuitized substrate which may be utilized as a chip carrier structure. The method involves the steps of providing a dielectric member and partially routing this member to define a temporary support portion therein. Metallization and circuitization may then occur, following which the temporary support portion is removed. This temporary support thus assures effective support for the photoresist used as part of the circuitization process. Thus, the photoresist is capable of being applied in sheetlike form for spanning the relatively small openings of the dielectric without sagging, bowing, etc., which may adversely impact subsequent processing steps.

Abstract: According to the present invention, a method of laminating at least two substrates together and circuitizing at least one surface of the laminate is provided. Pressure is exerted against opposite surfaces of each of said two substrates. An opening extends from a circuit-receiving surface of at least one of said substrates. A plug is provided which is configured to removably fit into said opening and has a support surface thereon which is substantially coplanar with the circuit-receiving surface when said plug is positioned in the opening. The plug is inserted in the opening with the support surface substantially coplanar with the circuit-receiving surface. The substrates are laminated by application of pressure on the opposite surfaces of the substrates. The circuit-receiving surface and the support surface are covered with a sheet of dry film photoresist to seal around the opening with said plug member supporting said sheet of photoresist in the region of the opening.

Abstract: A method of forming an I/C chip mounting module, and for mounting an I/C chip thereon, is disclosed. A rigid cap and substrate are provided. A bottomed cavity is routed in the cap, and the substrate has circuitry formed thereon. The cap and substrate are laminated together with bond pads, which connect to the circuitry being disposed in the cavity. After circuitization of the exposed surface of the cap and drilling and plating of vias, the material of the cap overlying the cavity is removed to expose the bond pads. Thereafter, an I/C chip is connect to the pads.

Abstract: According to the present invention, a method of laminating at least two substrates together and circuitizing at least one surface of the laminate is provided. Pressure is exerted against opposite surfaces of each of said two substrates. An opening extends from a circuit-receiving surface of at least one of said substrates. A plug is provided which is configured to removably fit into said opening and has a support surface thereon which is substantially coplanar with the circuit-receiving surface when said plug is positioned in the opening. The plug is inserted in the opening with the support surface substantially coplanar with the circuit-receiving surface. The substrates are laminated by application of pressure on the opposite surfaces of the substrates. The circuit-receiving surface and the support surface are covered with a sheet of dry film photoresist to seal around the opening with said plug member supporting said sheet of photoresist in the region of the opening.

Abstract: Simple, environmentally friendly developers and strippers are disclosed for free radical-initiated, addition polymerizable resists, cationically cured resists and solder masks and Vacrel photoresists. In all cases both the developers and the strippers include gamma butyrolactone, propylene carbonate and benzyl alcohol, optionally also including a minor amount of methanol, ethanol, isopropyl alcohol, propylene glycol monomethylacetate, ethylene glycol monomethyl ether, formamide, nitromethane, propylene oxide, or methyl ethyl ketone, acetone and water.